tag:blogger.com,1999:blog-18324475835054266622024-03-13T14:51:13.521-07:00Poly SPARC A Technical TravelogueAbishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.comBlogger110125tag:blogger.com,1999:blog-1832447583505426662.post-37684919701322452152013-08-25T10:30:00.001-07:002013-08-25T10:30:42.085-07:00Job Hunt 101 - Cover Letter how to?<div dir="ltr" style="text-align: left;" trbidi="on">
There will come different scenarios where you need to communicate with people. Writing a letter from scratch every time is time consuming. Having a template and modifying it to suit your purpose saves time and is easier. Here I have suggestions on what templates to prepare and samples.<br />
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You need to prepare templates for<br />
<br />
* Cover letter, <br />
* An email cover letter and <br />
* A linkedin inmail if you plan to use linkedin.<br />
<br />
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<b>COVER LETTER</b>The cover letter can be in the doc or pdf format, doc is preferable as computerised searches are done in doc files. Having a cover letter helps you in the following ways<br />
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<ol style="text-align: left;">
<li>When computer searches for relevant terms, chances are that it might find it in your cover letter if not on the resume. So do not replicate the resume data in the cover letter. Use the cover letter to compliment your resume.</li>
<li>If it passes through the computer search and your resume is visible to recruiter/HR, they will read your cover letter to understand better your qualifications.</li>
<li>It can help the hiring manager asses your strengths and if written well, is a showcase of your writing skills. </li>
</ol>
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The cover letter can be a page long with 3-4 paragraphs. You need to begin with your interest in the company, the position you are applying for and how you came to know about this position. Here is a comprehensive tutorial on writing cover letters.<br />
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<b>TUTORIAL ON WRITING COVER LETTERS</b> - <a href="http://www.wikihow.com/Write-a-Cover-Letter">http://www.wikihow.com/Write-a-Cover-Letter</a><br />
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<b>EMAIL COVER LETTER</b><br />
You might have to send emails to recruiters, HR, hiring manager, people you know, people you find in monster.com etc when you are forwarding your resume. Say you come across a position that interests you in DICE.com, you find the email of the person posting the resume. It is advantageous to fill in the DICE application form and also send in your resume to the email address mentioned. <br />
<br />
An email cover letter would help you introduce yourself and pique the hiring person's interest in you. It cannot be long winding stories it has to be precise and sharp. My cover letter had been evolving over the period of my application, the format I used is<br />
<ul style="text-align: left;">
<li>A sentence describing the position I am applying for, the company; expressing my interest</li>
<li>A sentence on my work experience</li>
<li>3-4 bullet points showing a few project experience. PLEASE NOTE I use the terms that are mentioned in the job description in these points so as to build interest in my profile. These are the terms the recruiter will be looking for.</li>
<li>My interest in talking to him</li>
<li>signature and dont forget the PHONE NUMBER</li>
</ul>
<br />
<b>SAMPLE</b><br />
<br />
I would like to express my interest in a position as anPOSITION at your company. My experience as POSITION 1 for 3 years and POSITION 2 for 2 years has provided me with the necessary skills required for the job. I am listing a few of them here<br />
<br />
<ul style="text-align: left;">
<li>Implemented Test Access Mechanism (TAM) and TPM (security hardware) onto openSPARCT1 SoC, contains more than a million lines of verilog RTL, used modelSIM, Synopsys design compiler, place and route. Synopsys Prime Time</li>
<li>Developed a complete System on chip - obstacle avoidance SoC, integrated open8, memory and a custom developed processor. Used Cadence tools - RTL Compiler, Virtuoso. LVS and DRC done.</li>
<li>Developed Design for Test (DFT) hardware to detect small delay defects.</li>
<li>Published 3 papers in international conferences.</li>
</ul>
<br />
I would like to talk to you regarding the position. Thank you very much for your time.<br />
Thanks,<br />
Signature<br />
Phone Number<br />
<br />
<br />
<b>LINKEDIN inmail</b><br />
This must not be wordy and must be precise since the person you are sending it to is assumed to know what he is looking for. Use the same format as email cover letter but put in relevant points without too much technical terms. Follow the cause action result format. <br />
<br />
<b>Sample </b><br />
Dear hiring manager,<br />
<br />
I came across a requirement for a <b>POSITION</b> at your company and I feel I am a good fit for this position.<br />
<br />
<ul style="text-align: left;">
<li>3 years experience as a <b>EE Engieer</b> with a masters in computer engineering from <b>University</b> (GPA 3.7/4).</li>
<li>Developed a Test access mechanism for System on Chips that reduced yield loss from >5% to 0.1%</li>
<li>Developed Design for Testability hardware that improved error coverage for small delay defects from 80% to 94%</li>
<li>Experienced in JTAG boundary scan 1149.1, BIST, MBIST, SoC Testing 1500, low power design techniques, asynchronous design techniques. Knowledge on Automatic Test Equipments (ATE). </li>
</ul>
<br />
I would like to be considered for this position. Kindly have a look at my profile.<br />
<br />
Thank you for your time.<br />
Name,<br />
Phone number <br />
<br />
Having these ready will make it easier to communicate with people.<br />
<br />
Best of luck.</div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-53163664656381624872013-08-11T23:17:00.004-07:002013-08-11T23:17:53.072-07:00Job Hunt 101 - Doc Prep - Resume How To?<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">The resume must be able to land you interview calls. Your resume must successfully be able to navigate through</span></span></div>
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<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Recruiters, consultants</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Human Resource</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Hiring Manager</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Technical Team</span></span></li>
</ol>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">I know you will ace the technical rounds if you are able to get through the hierarchy of recruiters, HR people etc. Your resume must help you climb this ladder. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">You can have an aesthetically pleasing resume/CV which does not have a lot of information on them but is very neat. This can help you with an academic position but in the industry, you are one amongst the million talented people who can get the job done. Here an aesthetically pleasing resume wont be able to help you. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Your resume must have a lot of data. This data must be able to satisfy the requirements of the Recruiters, must poke the interest of the HR and must show your accomplishments to the technical people who are going to be interviewing you. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Recruiters, Human Resource - </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Most recruiters are not going to be domain experts. The most probably dont understand what you have written in your resume. They might not even read it fully. They decide to continue/reject your application by doing a search for important terms required for the job. So being data intensive is good. Including the right keywords in your resume is the best way to navigate this course.</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Case in point, I found a job that seemed perfect for my qualifications but it got rejected at this level because they were not able to find an obscure acronym they were looking. I had not added it because it seemed too general and thought by looking at my work, they will realize that I was THE guy they wanted. Sadly they did not understand what I had written which is understandable since they are not working in my domain. I included the keyword and got selected for next round. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Hiring Manager, Technical People</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Being data intensive is good but being repetitive is not. When actual technical people read your resume, they would like to see results, problems solved, improvements and not just obscure terms and tools. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Here I am describing a format that will help you achieve these results. </span></span></div>
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<ol>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Format
</span></span><ol>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Name, contact phone number, address - Important so that people will be able to contact you</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Objective statement </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">work experience, chronological order starting with latest experince</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Education, chronological order starting with highest degree</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Software/Tools/Hardware skills</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Publications</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Certifications</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Achievements</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Reference</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Blog list - work sample</span></span></li>
</ol>
</li>
</ol>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Name, Contact phone number, address - Mail Address, Phone number so that people will be able to contact you</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Objective Statement - A concise statement that clearly states what industry you are targeting and what your objective is. Sample objective statement - "To secure a position with a leading semiconductor organization, that will enable me to use my strong</span></span></div>
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><span style="color: black; display: inline ! important; float: none; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">engineering skills and education background and ability to work well with people". </span></span></span><div style="color: black; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Sample objective statements can be found here - <a href="http://jobsearch.about.com/od/sampleresumes/a/sampleobjective.htm">http://jobsearch.about.com/od/sampleresumes/a/sampleobjective.htm</a></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Work Experience </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Recruiters are going to look if you have experience in the job you are applying. So list your experience in chronological order with the latest experience on top. A title and description are in order for each position you held.</span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Title: </span></span></li>
<li style="display: inline; list-style: none outside none;"><ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">You have to mention your designation, </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">company you work for and </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">your start and end dates, to quantify your experience. </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Ex - DFT Engineer, New York University ,08/2010 - 06/2013</span></span></li>
</ul>
</li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Description: After you mention these details, you need to describe the work you have been doing in that company. You will have worked on a number of projects, you should include a description for each of these projects. You can follow the CART rule when describing your work. </span></span></li>
<li style="display: inline; list-style: none outside none;"><ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Cause - The problem you worked on</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Action - What you did to address the problem</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Result - Quantifiable improvements you achieved.<span> </span><b>USE NUMBERS TO SHOW RESULTS</b>.</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Tools used </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Example -<b> Design for Testability hardware to improve Small Delay Defect coverage: Designed DfT hardware, developed placement algorithm that improves small delay defect coverage from 80% to 94%. Static and statistical timing analysis, timing closure was done, C and Perl was used.</b> </span></span></li>
</ul>
</li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Notes</span></span></li>
<li style="display: inline; list-style: none outside none;"><ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>Make sure you mention tools used in the description</b>, Recruiters recruit for a large number of positions and you cannot expect them to be knowledgeable in your domain. Most often the do not know understand your significant accomplishments. They search for tools and key words in your resume. Make sure you identify important key words pertaining to your domain and include them in your description. For example in the above statement I have used DfT, Static Timing Analysis, Timing closure, C and Perl which are highly searched keywords in my domain. </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">It is not possible to include all the tools, 3 letter acronyms you have worked with into your resume. I suggest you have<span> </span><b>one line in the end of your description where you can add tools, acronyms that you are familiar with and mentioned in the job description</b>. You modify this line to include important key terms mentioned in the job description. Presence of these key terms satisfies the recruiters enough to forward your resume to the next stage in the pipeline. Ex - Knowledge in interfaces PCI, PCIe, Ethernet and USB, Have used logic analyzer, oscilloscopes, multimeter. Note keywords PCI PCIe have been added because it is required in the job description and I have worked with them.</span></span></li>
</ul>
</li>
</ul>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Education</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">List your education in chronological order starting with highest degree on top. If you have a PhD, Masters or Bachelors, you do not have to include school information. Mention the </span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Degree,</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Major </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">University, </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Graduation year, </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">GPA - mention only if high. If you feel it is low, dont mention it. </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Ex - Master of Science, Computer Engineering, NYU Poly, 2013, 3.76</span></span></li>
</ul>
</div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Software/ Hardware Skills</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Make sure you mention the tools you have used and familiar with. Make this list as comprehensive as possible because recruiters are going to be searching for specific tools which you might have used. If you have it there, chances are that he will forward your resume</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Publications</span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">List your publications in chronological order. </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Include the ones you have submitted and waiting for results, mention that it has been submitted. </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Do not include work in progress.</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Format</span></span></li>
<li style="display: inline; list-style: none outside none;"><ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Authors - some one might know your co-authors,</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Name of the paper,</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Conference to which it is submitted to</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Year of publication </span></span></li>
</ul>
</li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Ex - Abishek Ramdas, Samah Saeed, Ozgur Sinanoglu. Design-for-Testability for Small Delay Defects. International Testing Conference, 2013, Submitted.</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">If you have submitted a Thesis, include the thesis in a separate section.</span></span></li>
</ul>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Certifications</span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">List in chronological order</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Certificate name</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Entity issuing the certificate</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Certificate number if applicable </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Ex - Nanoelectronics, Atomic Force Microscopy, Nanoscale Transistors, Purdue University, USA.</span></span></li>
</ul>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Achievements</span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Include affiliations, memberships - Ex Affiliated to IEEE</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">In achievements involving competition, express your rank as compared to total number of competitors in a competition</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Ex - Ranked 376 from over 1,50,000 engineers in All India Graduate Aptitude Test for Electrical Engineers.</span></span></li>
</ul>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Blog</span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Include the web address of your blog, make sure you create an hyperlink </span></span></li>
</ul>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Important Check List</span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Do not make your resume sound repetitive, do not include same information in different sections. </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">No spelling and grammar mistakes. Do a spell check</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Before sending out your resume make sure you look at the job description and add term, tools, 3 letter acronyms you feel important, to the extra line mentioned earlier.</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">The case is that you might be traveling around when searching for a job. Have a separate resume for different locations and send a resume that is closest to the job location.</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">You need your resume in doc and text format. Having it in PDF format makes it less searchable is what I hear. So uploading it in either doc format or text format is better for computerized searching of your resume.</span></span></li>
</ul>
</div>
</div>
</div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-26407099480104523742013-08-11T23:12:00.002-07:002013-08-12T04:39:16.375-07:00Job Hunt 101 - Doc Prep - Pre-Doc Prep<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Aim of this step is</span></span></div>
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<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Accessing your skills, experience and accomplishments. </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Getting data ready that you can use to fill online application forms easily</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Help in resume preparation</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Help in the HR, hiring manager round of interview</span></span></li>
</ul>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b><br /></b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>1. JOB SKILLS</b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>LISTING</b> - Start with the latest project and work your way down to the oldest project you can remember. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Example - </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">List of projects</span></span></div>
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<ol>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Testing chips using spare identical cores</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">DFT for SDD</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Etc....</span></span></li>
</ol>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>STATEMENTS</b> - For each of these projects collect the following information in a table</span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Title: </span></span></li>
<li style="display: inline; list-style: none outside none;"><ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">You have to mention your designation when doing the project, </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">company you work for and </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">your start and end dates, to quantify your experience. </span></span></li>
</ul>
</li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Statement: A brief desciprtion about the problem you worked on with numbers showing the effectiveness of your work</span></span></li>
</ul>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Example - consider</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Testing chips using spare identical cores - Developed Test access mechanism to test multi core chips </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">and </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Testing chips using spare identical cores - DFT Engineer, New York University ,08/2010 - 06/2013 - Developed a test access mechanism and design for testability scheme to test multi-core chips. I was able to reduce the yield loss from 6% to 0.1%, saving upto $1.5M annually. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b><br /></b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>See how the second statement with numbers improve the strength of your statement.</b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b><br /></b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>2. PERSONAL SKILLS</b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>LISTING -</b> Identify 10 personal skills that you feel you possess <a href="http://www.illinoisworknet.com/vos_portal/Archives/Documents/Personal_Skills_Checklist.htm">http://www.illinoisworknet.com/vos_portal/Archives/Documents/Personal_Skills_Checklist.htm</a></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Of these 10 choose 5 skills that applies most to you</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>STATEMENTS -</b> Write statements that describe the situation where you have used the skill, Use numbers to show effectiveness of work. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>3. How I am different from others?</b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Have 3-4 statements why you think you are different from others. You can state your skills, accomplishments etc</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Example - </span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Extensive hands-on knowledge in VLSI system design, architecture and Testing.</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Fluent with ASIC Design flow, worked with Cadence and Synopsys design tools.</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Published 3 papers at well known conferences in the field of VLSI Testing.</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Knowledgable in device physics, quantum mechanics, atomic transport, nanoscale device modeling. </span></span></li>
</ul>
<div>
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>4. Keyword List</b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">A list of keywords that can be used to search for positions on various job boards. </span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Sit for some time and brainstorm important terms, acronyms, tools, designations, languages, concepts that you think</span></span></div>
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<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">important in your domain</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">you have experience with</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">are needed in the industry</span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Is contained in search terms for common positions in the industry</span></span></li>
</ul>
<div>
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Ex - My domain as DFT Engineer, These are common terms I use to search for positions </span></span></div>
</div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Cadence, encounter, virtuoso, RTL compiler, Synopsys, Tetramax, Design compiler, RTL, vhdl, verilog, verification, synthesis, place and route, layout, clock tree, openSPARC, DFT, DFX, ATPG, BIST, Design for test, boundary scan, VLSI, Testing, FPGA, VIrtex, spartan, modelSIm, Xilinx, ISE, EDk, chipscope, SRAM, PIC, microcontroller, MPLAB, assembly, mpasm, C, I2C, SPI, Ethernet, USB, Perl, Matlab, signal processing, JMP, SAS, logisim, gate level simulation, SoC</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>5. Transcripts, Certificates, Publications, Thesis, Project documents</b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">In a folder, collect all your transcripts,certificates, Publications, Thesis and Project documents. For certain positions, You might need to submit a few of these documents. They can be used as a reference for later on.</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>6. List of Companies</b></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Brainstorm a list of companies in your domain that you would like to be placed in a spreadsheet.</span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
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<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>7. List of References</b></span></span></div>
<div style="color: black; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Create a spreadsheet with atleast 3 references with their </span></span></div>
<div style="color: black; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<ul>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">names, </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">designation, </span></span></li>
<li><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">phone number</span></span></li>
</ul>
</div>
<div style="color: black; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><b>8. List of Contacts</b></span></span></div>
<div style="color: black; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Brainstorm a list of people you know and who can help you in forwarding your resume internally. Have an excel sheet with 3 columns, Company, Name, designation, contact information (email, phone) and add them to a spreadsheet.</span></span></div>
<div style="color: black; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">
</span></span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-53934838426621649662013-08-11T23:08:00.000-07:002013-08-11T23:18:36.857-07:00Job Hunt 101 - Document Preparation<div dir="ltr" style="text-align: left;" trbidi="on">
<span style="font-family: Verdana,sans-serif;">The first step of the preparation process is to get your documents ready and easily available when needed. There are a number of documents we need to have for a successful application. Here we discuss the documents and how they can be prepared. </span><br />
<br />
<span style="font-family: Verdana,sans-serif;">The steps involved are</span><br />
<ol style="text-align: left;">
<li><a href="http://abishekramdas.blogspot.com/2013/08/job-hunt-101-doc-prep-pre-doc-prep.html"><span style="font-family: Verdana,sans-serif;">Pre-document preparation</span></a><a href="http://abishekramdas.blogspot.com/2013/08/job-hunt-101-doc-prep-pre-doc-prep.html"></a></li>
<li><a href="http://abishekramdas.blogspot.com/2013/08/job-hunt-101-doc-prep-resume-how-to.html"><span style="font-family: Verdana,sans-serif;">Resume</span></a> </li>
<li><span style="font-family: Verdana,sans-serif;">Cover letter</span> </li>
<li><span style="font-family: Verdana,sans-serif;">E-Mail cover letter </span></li>
<li><span style="font-family: Verdana,sans-serif;">Linkedin in-mail letter</span> </li>
</ol>
<span style="font-family: Verdana,sans-serif;">Click on the links to get started. </span><br />
<span style="font-family: Verdana,sans-serif;"><br /></span>
<span style="font-family: Verdana,sans-serif;">Thanks,</span><br />
<span style="font-family: Verdana,sans-serif;">Abishek</span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-65450316165230067002013-08-11T23:02:00.000-07:002013-08-11T23:18:46.222-07:00Job Hunt 101<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
</div>
<div style="text-align: justify;">
<div style="color: black; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-family: Verdana,sans-serif; font-size: small;">Hello, </span></div>
<div style="color: black; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-family: Verdana,sans-serif; font-size: small;"><br /></span></div>
<div style="color: black; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-family: Verdana,sans-serif; font-size: small;">I am a new college graduate and was looking for my first job. I had to walk, skip, fall and learn from my mistakes before I got my dream job. It took me a lot of preparation and a lot more patience for me to land it. I understand how difficult it is for you and so I am creating a series of guides that has tips and information on what I had learnt in the process of searching for a job. I list strategies that might be useful for you to turn your luck around. These tips are aimed at getting the maximum benefit of every opportunity that comes our way. Being prepared is the best way to land the job. </span></div>
<div style="color: black; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-family: Verdana,sans-serif; font-size: small;"><br /></span></div>
<div style="color: black; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-family: Verdana,sans-serif; font-size: small;">Aim</span></div>
<div style="color: black; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<ul>
<li><span style="font-family: Verdana,sans-serif; font-size: small;">To provide you with tips and tricks that I had learnt in the process of searching for a job. </span></li>
<li><span style="font-family: Verdana,sans-serif; font-size: small;">To learn from your feedback and experience.</span></li>
</ul>
</div>
<div style="color: black; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<span style="font-family: Verdana,sans-serif; font-size: small;">I plan to address the following topics which have subtopics in them (click on them to view)</span></div>
<div style="color: black; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;">
<ul>
<li><span style="color: blue; font-size: small;"><a href="http://abishekramdas.blogspot.com/2013/08/job-hunt-101-document-preparation.html"><span style="font-family: Verdana,sans-serif;">Document preparation</span></a></span></li>
<li><span style="font-family: Verdana,sans-serif; font-size: small;">Application</span></li>
<li><span style="font-family: Verdana,sans-serif; font-size: small;">Interview Preparation</span></li>
<li><span style="font-family: Verdana,sans-serif; font-size: small;">The Interview</span></li>
<li><span style="font-family: Verdana,sans-serif; font-size: small;">Mental strength</span></li>
</ul>
<div>
<span style="font-family: Verdana,sans-serif; font-size: small;">I wish you the best of luck in your journey. </span></div>
<div>
</div>
<div>
<span style="font-family: Verdana,sans-serif; font-size: small;">Thanks,</span></div>
<div>
<span style="font-family: Verdana,sans-serif; font-size: small;">Abishek </span></div>
<div>
</div>
<div>
<span style="font-family: Verdana,sans-serif; font-size: small;">PS - This is a work in progress </span></div>
</div>
</div>
<span style="font-family: Verdana,sans-serif; font-size: small;">
</span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-30513806001909349922013-06-22T11:42:00.003-07:002013-06-22T12:05:27.492-07:00Scan Insertion<span style="font-family: Verdana,sans-serif;">Hello,</span><br />
<span style="font-family: Verdana,sans-serif;"><br /></span>
<span style="font-family: Verdana,sans-serif;">Scan insertion is the process of converting the flip flops present in a circuit into scan flip flops</span><br />
<span style="font-family: Verdana,sans-serif;"><span style="font-size: small;">The flip-flops in the circuit, shown in Figure, are connected together in a chain to form a shift register, also called scan chain. This makes all flip-flops in the circuit controllable and observable leaving behind only the combinational logic to be tested. </span></span><br />
<div class="separator" style="clear: both; text-align: center;">
<a href="http://2.bp.blogspot.com/-nyafSitw2As/UcXpnuojeRI/AAAAAAAAAGo/j8O0PqdbZn8/s1600/scan_insertion.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="http://2.bp.blogspot.com/-nyafSitw2As/UcXpnuojeRI/AAAAAAAAAGo/j8O0PqdbZn8/s1600/scan_insertion.png" height="72" width="400" /></a></div>
<br />
<span style="font-family: Verdana,sans-serif;"><span style="font-size: small;">During scan mode, the test vectors are shifted into (scan-in) the scan chain by shift operations. The test vectors are then applied to the combinational logic and the response is clocked back into the flip-flops. The response is then shifted out (scan-out) from the scan chain to test as the next test vector is being scanned in. This DFT converts the difficult to test sequential circuit into a fully combinational circuit. </span></span><br />
<div class="separator" style="clear: both; text-align: center;">
<a href="http://3.bp.blogspot.com/-Y0J2ATmoz78/UcXqpHlZR5I/AAAAAAAAAG4/PabA9xFXi6k/s1600/scan_chain.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="http://3.bp.blogspot.com/-Y0J2ATmoz78/UcXqpHlZR5I/AAAAAAAAAG4/PabA9xFXi6k/s1600/scan_chain.png" height="185" width="320" /></a></div>
<br />
<span style="font-family: Verdana,sans-serif;"><span style="font-size: small;"><span style="font-size: small;">For
large designs, the long chain is split into several smaller chains in
order to cope with the large number of test patterns. The chains can
have different lengths and the depth is defined by the length of the
longest chain. This splitting of the scan chain increases the test speed
because several chains can now be operated in parallel but has the
added cost of additional pins and channels. </span></span></span><br />
<br />
<span style="font-family: Verdana,sans-serif;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;">You can us<span style="font-size: small;">e commercial tools<span style="font-size: small;"> like Synopsys Tetramax to do scan insertion for <span style="font-size: small;">you. Otherwise you can write your own script that does scan insertion<span style="font-size: small;">. <span style="font-size: small;">Here i<span style="font-size: small;">s a script that converts DFF t<span style="font-size: small;">o Sc<span style="font-size: small;">an DFF in a verilog file. T<span style="font-size: small;">he n<span style="font-size: small;">ame of <span style="font-size: small;">the scan flip-flop <span style="font-size: small;">and necessary connections can be identifie<span style="font-size: small;">d using the library<span style="font-size: small;">. Flip flops are identified<span style="font-size: small;">, their names changed<span style="font-size: small;">, connections re-connected and additional pins are added at the primary input.</span></span></span></span></span></span></span></span></span></span></span></span></span></span></span></span></span></span></span></span><br />
<br />
<span style="font-family: Verdana,sans-serif;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;">PERL SCRIPT THAT DOES SCAN INS<span style="font-size: small;">ER<span style="font-size: small;">TION</span></span></span></span></span></span></span></span></span></span></span><br />
<span style="font-family: Verdana,sans-serif;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"><span style="font-size: small;"> </span></span></span> </span></span></span></span></span></span></span></span> <br />
<pre style="background-image: URL(http://2.bp.blogspot.com/_z5ltvMQPaa8/SjJXr_U2YBI/AAAAAAAAAAM/46OqEP32CJ8/s320/codebg.gif); background: #f0f0f0; border: 1px dashed #CCCCCC; color: black; font-family: arial; font-size: 12px; height: auto; line-height: 20px; overflow: auto; padding: 0px; text-align: left; width: 99%;"><code style="color: black; word-wrap: normal;"> #!/usr/bin/perl
#scan_insertion.plx
use warnings;
use Data::Dumper;
use List::Util qw(min);
my $bench_file = $ARGV[0];
my $file_name;
#Test netlist file
if($bench_file =~ /(.*).v/){
$file_name = $1;
}
else{
print "Format of bench file name: circuit_name.v \n example : s1423.v\n";
}
$file_name_scan_ins = $file_name.'_scan_inserted.v';
open($FILEREAD, $bench_file) or die "could not open file to read";
open($FILEWRITE, '>', $file_name_scan_ins) or die "Could not open\n";
#Read Netlist File - count #FF
while(<$FILEREAD>){
my $INPUT_DATA = $_;
chomp($INPUT_DATA);
if($INPUT_DATA =~ m/^\s*(DFFX1)\s*(.*)\s*\(\.CK\((.*)\),\s*\.D\((.*)\),\s*\.Q\((.*)\)\);$/){
$count++;
}
}
close(FILEREAD);
#Modify netlist
$max_count = $count;
my $modified_data;
my $prev_op;
open($FILEREAD, $bench_file) or die "could not open file to read";
while(<$FILEREAD>){
$INPUT_DATA = $_;
chomp($INPUT_DATA);
if($INPUT_DATA =~ /module\s*(.*)\s*\((.*)\);/){
$circuit_name = $1;
print $FILEWRITE "module "."$1 "."($2,scan_data_in,scan_data_out,scan_enable);\n";
}
elsif($INPUT_DATA =~ /^\s*input\s*(.*);/){
print $FILEWRITE "input ".$1.",scan_data_in,scan_enable;"."\n";
}
elsif($INPUT_DATA =~ /^\s*output\s*(.*);/){
print $FILEWRITE "output ".$1.",scan_data_out;"."\n";
}
elsif($INPUT_DATA =~ m/^\s*(DFFX1)\s*(.*)\s*\(\.CK\((.*)\),\s*\.D\((.*)\),\s*\.Q\((.*)\)\);$/){
if($count == $max_count){
print $FILEWRITE "S_DFFX1"." ".$2."(.CK($3),.D($4),.SE(scan_enable),.SI(scan_data_in),.Q($5));\n";
$prev_op = $5;
}
else{
print $FILEWRITE "S_DFFX1"." ".$2."(.CK($3),.D($4),.SE(scan_enable),.SI($prev_op),.Q($5));\n";
$prev_op=$5;
if($count == 1){
print $FILEWRITE "BUFX1 scan_buff_op (.A($5),.Y(scan_data_out));\n"
}
}
$count--;
}
else{
print $FILEWRITE $INPUT_DATA."\n";
}
}
close(FILEREAD);
close(FILEWRITE);
</code></pre>
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Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-66048990221449603652013-06-22T10:32:00.000-07:002013-06-22T10:32:07.983-07:00Path TraceHello,<br />
<br />
I am posting an old program here that was written by me to trace different paths in a circuit. It is written in Perl and works for verilog (.v) files.<br />
<br />
The program recursively iterates through every path in the circuit and it prints out the gates encountered en-route. It is useful if you are calculating a metric for each gate/wire <br />
<br />
This is a way to NOT write a program. The program, as I found out later, is very slow because<br />
<ul>
<li>It does not build the data structure for gates that makes traversing easier</li>
<li>It works with gate names instead of numeric abstractions which are easier to deal with. </li>
</ul>
The better way to traverse through a circuit is to build a data structure for each gate encountered. Each gate should be assigned a number and there must be arrays in the data structure that holds information on the gates at its input and output. This makes traversing in both directions easier.<br />
<br />
<b>Sample data structure</b><br />
struct gate{<br />
char name[];<br />
int num_in;<br />
int num_out;<br />
int in[];<br />
int out[];<br />
.<br />
.<br />
} <br />
<br />
You need to traverse the netlist once to fill in the data structures and you are good to go.<br />
<br />
I cannot post the better program here because it was not written by me. So I post my old version of path trace here.
<br />
<pre style="background-image: URL(http://2.bp.blogspot.com/_z5ltvMQPaa8/SjJXr_U2YBI/AAAAAAAAAAM/46OqEP32CJ8/s320/codebg.gif); background: #f0f0f0; border: 1px dashed #CCCCCC; color: black; font-family: arial; font-size: 12px; height: auto; line-height: 20px; overflow: auto; padding: 0px; text-align: left; width: 99%;"><code style="color: black; word-wrap: normal;"> #!/usr/bin/perl
#Path_Trace.plx
use warnings;
use Data::Dumper;
use strict;
use List::Util qw(min);
my $bench_file = $ARGV[0];
my $file_name;
my $circuit_name;
my $element;
my @input_array;
my @output_array;
my @wire_array;
my @gates;
my @sorted_gates;
my @wire_struct;
my @input_list_struct;
my @input_list_struct_2;
my @output_list_struct;
my @gate_queue;
#my @fanout_test;
my $num_inputs=0;
my $num_outputs=0;
my $num_wires=0;
my $num_gates=0;
my $gate_name_temp;
my $gate;
my $line;
my $role;
my $inp;
my $inp_test;
#Test netlist file
if($bench_file =~ /(.*).v/)
{
$file_name = $1;
}
else
{
print "Format of bench file name: circuit_name.v \n example : s1423.v\n";
}
#Read Netlist File
while(<>)
{
my $INPUT_DATA = $_;
chomp($INPUT_DATA);
{
#MODULE NAME
if($INPUT_DATA =~ /module (.*) (.*);/)
{
$circuit_name = $1;
print "circuit name = $circuit_name\n";
}
#INPUT OUTPUT WIRES
if($INPUT_DATA =~ m/^\s*input (.*);/)
{
@input_array = split /,/, $1;
}
if($INPUT_DATA =~ m/^\s*output (.*);/)
{
@output_array = split /,/, $1;
}
if($INPUT_DATA =~ m/^\s*wire (.*);/)
{
@wire_array = split /,/, $1;
}
my @wire1;
my @wire2;
my @wire3;
my $gate_name_temp;
my $gate;
my $line;
my $role;
#AND, OR, NAND, NOR, XOR
if($INPUT_DATA =~ m/^\s*(NAND2X1)\s*(.*)\s*\(\.Y\((.*)\),\.A\((.*)\),\.B\((.*)\)\);$/)
{
push @gates,
{
element => "gate",
num_inputs => 2,
gate_type => "$1",
gate_name => "$2",
output =>
{
element => "wire",
wire_name => "$3",
sa0 => 1,
sa1 => 1,
level => 0,
wire_delay =>0,
},
input_1 =>
{
element => "wire",
wire_name => "$2_$4",
sa0 => 1,
sa1 => 1,
level => 0,
wire_delay => 0,
},
input_2 =>
{
element => "wire",
wire_name => "$2_$5",
sa0 => 1,
sa1 => 1,
level => 0,
wire_delay => 0,
},
processed => 0,
gate_delay => 2,
gate_level => -1
};
}
#INV, BUF
#DE - Doesnt Exist
#renaming the gates at inputs of the gates for fanouts
if($INPUT_DATA =~ m/^\s*(INVX1|BUFX1) (.*) \(\.Y\((.*)\),\.A\((.*)\)\);$/)
{
$gate_name_temp = $2;
push @gates,
{
element => "gate",
num_inputs => 1,
gate_type => "$1",
gate_name => "$2",
output =>
{
element => "wire",
wire_name => "$3",
sa0 => 1,
sa1 => 1,
level => 0,
wire_delay => 0,
},
input_1 =>
{
element => "wire",
wire_name => "$2_$4",
sa0 => 1,
sa1 => 1,
level => 0,
wire_delay => 0,
},
processed => 0,
gate_delay => 1,
gate_level => -1
};
}
}
}
#File Read complete
#wire struct holds fault data for all wires
#input_list_struct is used for levelization
for $element (@input_array){
push @wire_struct, {element => "wire",wire_name => "$element", sa0 => 1, sa1 =>1, level => 0,wire_delay=>0};
push @input_list_struct, {element => "wire",wire_name => "$element", sa0 => 1, sa1 => 1, level => 0,wire_delay=>0};
push @input_list_struct_2, {element => "wire",wire_name => "$element", sa0 => 1, sa1 => 1, level => 0,wire_delay=>0};
}
for $element (@wire_array){
push @wire_struct, { element => "wire",wire_name => "$element", sa0 => 1, sa1 =>1, level => -1,wire_delay=>0};
}
for $element (@output_array){
push @wire_struct, { element => "wire",wire_name => "$element", sa0 => 1, sa1 =>1, level => -1,wire_delay=>0};
push @output_list_struct, {element => "wire",wire_name => "$element", sa0 => 1, sa1 => 1, level => 0,wire_delay=>0};
}
$num_gates = scalar @gates;
my $index=0;
#gate_processed = 2 then all inputs are processed
#shift gate into the queue if even one of the inputs processed
while($num_gates != 0)
{
for my $gate(@gates){
for my $inp (@input_list_struct){
my $inp_test = $inp->{wire_name};
if(($gate->{input_1})->{wire_name} =~ m/$inp_test$/){
$gate->{processed}++;
if($gate->{processed}==1){
unshift(@gate_queue,$gate);
}
if($gate->{processed}>1){
$gate->{processed}=$gate->{num_inputs};
}
}
if(($gate->{num_inputs}!=1)){
if(($gate->{input_2})->{wire_name} =~ m/$inp_test$/){
$gate->{processed}++;
if($gate->{processed}==1){
unshift(@gate_queue,$gate);
}
}
if($gate->{processed}>1){
$gate->{processed}=$gate->{num_inputs};
}
}
}
}
#if both inputs of the gates are processed, then calculate the level of the gate
#if only one of the inputs are processed, then add the gate to the end
my $num_gate_queue = scalar @gate_queue;
while ($num_gate_queue != 0)
{
$gate = pop(@gate_queue);
if($gate->{processed}==$gate->{num_inputs}){
if($gate->{num_inputs}==2){
if(($gate->{input_1}->{level})>($gate->{input_2}->{level})){
$gate->{gate_level} = ($gate->{input_1}->{level});
}
else{
$gate->{gate_level} = ($gate->{input_2}->{level});
}
$gate->{gate_level}++;
$gate->{output}->{level}=$gate->{gate_level};
unshift(@input_list_struct,$gate->{output});
$num_gate_queue--;
$num_gates--;
}
elsif($gate->{num_inputs}==1){
$gate->{gate_level} = $gate->{input_1}->{level};
$gate->{gate_level}++;
$gate->{output}->{level}=$gate->{gate_level};
unshift(@input_list_struct,$gate->{output});
$num_gate_queue--;
$num_gates--;
}
}
else{
unshift(@gate_queue,$gate);
$num_gate_queue--;
}
}
#the updated levels of the wires are present in input_list_struct
#update the fanouts of the gate with the levels from this struct
for $gate(@gates){
for $inp (@input_list_struct){
$inp_test = $inp->{wire_name};
if(($gate->{input_1})->{wire_name} =~ m/$inp_test$/){
$gate->{input_1}->{level} = $inp->{level};
}
if($gate->{num_inputs}!=1){
if(($gate->{input_2})->{wire_name} =~ m/$inp_test$/){
$gate->{input_2}->{level} = $inp->{level};
}
}
}
}
}
print "gate: level\n";
for $gate (@gates){
print "$gate->{gate_name}: $gate->{gate_level}\n";
}
print "\n\nPaths and Delays\n";
#Path Trace Variable Decl
my $wire;
my $inp_count = scalar @input_list_struct_2;
my $path_count;
my @fanout_array;
my $path_complete=0;
my @path_array;
my @tmp_current_path;
my $depth=-1;
my $tmp_num_fanouts=0;
my @num_fanouts;
my $num_paths=0;
my @saved_restore;
my @path_delay;
# End path trace variable decl
while($inp_count !=0){
my @current_path;
$wire = pop @input_list_struct_2;
$inp_count--;
$depth = 0;
$num_fanouts[$depth]=1;
push @current_path,$wire;
$tmp_num_fanouts=0;
for $gate (@gates){
if(($gate->{input_1})->{wire_name} =~ m/$wire->{wire_name}/){
$tmp_num_fanouts++;
push @fanout_array,$gate;
}
elsif($gate->{num_inputs}!=1){
if(($gate->{input_2})->{wire_name} =~ m/$wire->{wire_name}/){
$tmp_num_fanouts++;
push @fanout_array,$gate;
}
}
} #all fanouts are in the fanout array now pop the fanout array and continue the process
#more than 1 fanout need to save the values for future use
if($tmp_num_fanouts>1){
$depth++;
$num_fanouts[$depth] = $tmp_num_fanouts;
#save current path for the future
my $i=0;
for $element (@current_path){
$tmp_current_path[$depth][$i]=$element;
$i++;
}
$saved_restore[$depth]=$i;
}
while((scalar @fanout_array)!=0){
$path_complete=0;
#pop the next gate in the stack
$gate = pop @fanout_array;
#when the number of fanouts in the depth is over, reduce the depth
#push the new gate in the current path
push @current_path,$gate;
#trace the wire
$wire = $gate->{output};
my $flag=0;
for my $element2 (@output_list_struct){
if($wire->{wire_name} =~ m/$element2->{wire_name}/){
$flag = 1;
}
}
if($flag == 0){
push @current_path,$wire;
}
while(!$path_complete){
#reached output? path completed
for $element (@output_list_struct){
if($wire->{wire_name} =~ m/$element->{wire_name}/){
$path_complete=1;
$num_paths++;
push @current_path,$wire;
my $j=0;
my $i=$num_paths-1;
for $element (@current_path){
$path_array[$i][$j]=$element;
$j++;
}
#check iteratively if all the previous depth paths are exhausted
if($num_fanouts[$depth]>1){
$num_fanouts[$depth]--;
#resotring current path for a new path
my $i=0;
splice(@current_path,0);
while($i<$saved_restore[$depth]){
for $element ($tmp_current_path[$depth][$i]){
$current_path[$i]=$element;
$i++;
}
}
}
elsif($depth!=0){
$depth--;
#if the number of fanouts at this depth is greater than 1 then restore else continue with the next cycle
while($depth!=0){
if($num_fanouts[$depth]>1){
#remove if wrong
$num_fanouts[$depth]--;
my $i=0;
splice(@current_path,0);
while($i<$saved_restore[$depth]){
for $element ($tmp_current_path[$depth][$i]){
$current_path[$i]=$element;
$i++;
}
}
last;
}
else{
$depth--;
}
}
}
last;
}
}
#if path is not completed find fanouts
$tmp_num_fanouts=0;
if(!$path_complete){
for $gate (@gates){
if(($gate->{input_1})->{wire_name} =~ m/$wire->{wire_name}/){
push @fanout_array,$gate;
$tmp_num_fanouts++;
}
elsif($gate->{num_inputs}!=1){
if(($gate->{input_2})->{wire_name} =~ m/$wire->{wire_name}/){
push @fanout_array,$gate;
$tmp_num_fanouts++;
}
}
}#all fanouts are in the fanout array now pop the fanout array and continue the process
if($tmp_num_fanouts > 1){
$depth++;
my $i=0;
for $element (@current_path){
$tmp_current_path[$depth][$i]=$element;
$i++;
}
$saved_restore[$depth]=$i;
$num_fanouts[$depth] = $tmp_num_fanouts;
}
$gate = pop(@fanout_array);
$wire = $gate->{output};
# push @current_path,$wire;
push @current_path,$gate;
}
}
}
}
for(my $i=0;$i<$num_paths;$i++){
$path_delay[$i] = 0;
for(my $j=0;$j<$#{$path_array[$i]}+1;$j++){
if($path_array[$i][$j]->{element} =~ m/gate/){
print $path_array[$i][$j]->{gate_name}."->";
$path_delay[$i] = $path_delay[$i]+$path_array[$i][$j]->{gate_delay};
}
elsif($path_array[$i][$j]->{element} =~ m/wire/){
print $path_array[$i][$j]->{wire_name}."->";
$path_delay[$i] = $path_delay[$i]+$path_array[$i][$j]->{wire_delay};
}
}
print "\t\t delay: ".$path_delay[$i]."\n";
}
</code></pre>
Good Luck,
AbishekAbishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-82254437087781043442013-03-09T06:47:00.000-08:002013-03-16T15:55:34.481-07:00Aasai Mugam Maranthu Poche<div dir="ltr" style="text-align: left;" trbidi="on">
<span style="font-family: Verdana,sans-serif;">Bharathiyar, for tamil people, needs no introduction. He was a great tamil poet and a contemporary of Rabindranath Tagore. The world had the good fortune of reading Tagore's beautiful lines as many were written in English but was not so lucky when it came to the poems of Bharathi. </span><br />
<br />
<span style="font-family: Verdana,sans-serif;">Maybe Bharathi deserves better than what we can offer.</span><br />
<br />
<span style="font-family: Verdana,sans-serif;">Here is one of his songs, translated with not so much justice done. He lost his mother at a very early age. When the only picture he had that reminded him of her gets lost, to the love of his life, poetry, he says</span><br />
<span style="font-family: Verdana,sans-serif;"><br /></span>
<span style="font-family: Verdana,sans-serif;">I have forgotten the lovely face,<br />To whom can I show my grief my dear friend?<br />Even if my heart remembers the vivd love, <br />why has my memory failed to keep the face intact, my dear friend?<br /><br />The bee that thinks no more of nectar,<br />The flower that consigns the sun to oblivion,<br />The vegetation that fails to recollect the rain, Has never existed. <br />Why am I the aberration my dear friend?<br /><br />What purpose do these eyes serve <br />if I cannot remember the beautiful face<br />I do not even posses a picture, you know it<br />what is my plea to live, my dear friend?</span><br />
<br />
<br />
<iframe allowfullscreen="" frameborder="0" height="315" src="http://www.youtube.com/embed/xCCkfrB4qak" width="420"></iframe>
<span style="font-family: Verdana,sans-serif;"><br /></span>
<span style="font-family: Verdana,sans-serif;"><br /></span>
<span style="font-family: Verdana,sans-serif;"><br /></span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-69984035158711809432012-12-24T10:06:00.000-08:002012-12-24T10:06:02.909-08:00Levelization of circuits<div dir="ltr" style="text-align: left;" trbidi="on">
<div dir="ltr" style="text-align: left;" trbidi="on">
<span style="font-family: Verdana, sans-serif; font-size: small;">Hello</span><span style="font-size: small;">,</span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">When working with benchmark circuits, it is convenient to levelize the gates and work with levels. This is useful when you want to calculate some metric for all gates or wires. It is efficient than recursively traversing through all wires, gates, and fanouts. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Here I upload a program that levelizes the iscas bench marks. </span><span style="font-size: small;"> It is written in perl.<span style="font-family: Verdana, sans-serif;"> Use it the way you see fit and edit it if you find mistakes.</span></span><br />
<span style="font-size: small;"><br /></span>
<br />
<div style="margin-bottom: 0in;">
<br />
<style type="text/css">
<!--
@page { margin: 0.79in }
P { margin-bottom: 0.08in }
-</style><span style="font-family: Verdana,sans-serif;"><b>Levelization </b></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;">1. Assign level number 0 to all primary
inputs
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;">2. For each PI fanout
</span></div>
<ul style="text-align: left;">
<li><span style="font-family: Verdana,sans-serif;">Label that circuit line with level
number of the PI</span><span style="font-family: Verdana,sans-serif;"> </span></li>
<li><span style="font-family: Verdana,sans-serif;">Queue the logic gate driven by that
fanout line (I need a queue)
</span></li>
</ul>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;">3. While queue is not empty
</span></div>
<ul style="text-align: left;">
<li><span style="font-family: Verdana,sans-serif;"> dequeue the next logic gate in the
queue</span><span style="font-family: Verdana,sans-serif;"> </span></li>
<li><span style="font-family: Verdana,sans-serif;">If all of the gate fanins are
labeled with level numbers, then label the logic gate and its fanouts
with maximum of input levels + 1. Queue all fanouts of the logic
gate. Otherwise requeue the logic gate. </span></li>
</ul>
</div>
<div style="margin-bottom: 0in;">
<br />
<b><span style="font-family: Verdana,sans-serif;">Algorithm - Levelization</span></b></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;">loop
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;">inputlist - list of primary inputs
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;">for all gates
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"> if either of input of gates is present
in the inputlist,
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"> add the gate to the queue
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;">for the gates in the queue
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"> dequeue the gate
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"> if all the inputs of the gates have
levels assigned (level is not -1) then
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"> level(gate)=max(level of inputs)+1,
level(output wire) = max(level of inputs)+1
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"> push outputwire into input list
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"> if all inputs of gate do not have
levels assigned
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"> push the gate to the end of the
queue.
</span></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;">goto loop </span></div>
<div style="margin-bottom: 0in;">
<br /></div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana,sans-serif;"><b>How to run: </b>perl levelization.plx test_3.v </span><br />
<br />
<b><span style="font-family: Verdana,sans-serif;">Sample: test_3.v </span></b><br />
<span style="font-family: Verdana,sans-serif;">module test_3 (A1,B1,C1,D1,O1,O2,O3); </span><br />
<span style="font-family: Verdana,sans-serif;">input A1,B1,C1,D1; </span><br />
<span style="font-family: Verdana,sans-serif;">output O1,O2,O3; </span><br />
<span style="font-family: Verdana,sans-serif;">wire Z1,Z2,Z3,Z4; </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2X1 NAND2_1 (.Y(Z1),.A(C1),.B(D1)); </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2X1 NAND2_2 (.Y(Z2),.A(B1),.B(Z1)); </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2X1 NAND2_3 (.Y(Z3),.A(A1),.B(Z2)); </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2X1 NAND2_4 (.Y(Z4),.A(Z2),.B(Z1)); </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2X1 NAND2_5 (.Y(O3),.A(C1),.B(D1)); </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2X1 NAND2_6 (.Y(O1),.A(Z3),.B(Z4)); </span><br />
<span style="font-family: Verdana,sans-serif;">BUFX1 BUF1_1 (.Y(O2),.A(Z4)); </span><br />
<span style="font-family: Verdana,sans-serif;">endmodule </span><br />
<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="http://4.bp.blogspot.com/-WmNLujquOFA/UNiX5YYGvvI/AAAAAAAAAGM/qwhWNt0IofM/s1600/SDD_sample_circuit_buffer.png" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="148" src="http://4.bp.blogspot.com/-WmNLujquOFA/UNiX5YYGvvI/AAAAAAAAAGM/qwhWNt0IofM/s320/SDD_sample_circuit_buffer.png" width="320" /></a></div>
<br />
<br />
<b><span style="font-family: Verdana,sans-serif;">Output </span></b><br />
<span style="font-family: Verdana,sans-serif;">gate: level </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2_1: 1 </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2_2: 2 </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2_3: 3 </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2_4: 3 </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2_5: 1 </span><br />
<span style="font-family: Verdana,sans-serif;">NAND2_6: 4 </span><br />
<span style="font-family: Verdana,sans-serif;">BUF1_1: 4
</span></div>
<div style="margin-bottom: 0in;">
<br /></div>
<div style="margin-bottom: 0in;">
<br /></div>
<span style="font-family: Verdana,sans-serif;"></span>
<br />
<pre style="background-image: URL(http://2.bp.blogspot.com/_z5ltvMQPaa8/SjJXr_U2YBI/AAAAAAAAAAM/46OqEP32CJ8/s320/codebg.gif); background: #f0f0f0; border: 1px dashed #CCCCCC; color: black; font-family: arial; font-size: 12px; height: auto; line-height: 20px; overflow: auto; padding: 0px; text-align: left; width: 99%;"><code style="color: black; word-wrap: normal;"> #!/usr/bin/perl
#levelization.plx
use warnings;
use Data::Dumper;
use strict;
my $bench_file = $ARGV[0];
my $file_name;
my $circuit_name;
my $element;
my @input_array;
my @output_array;
my @wire_array;
my @gates;
my @sorted_gates;
my @wire_struct;
my @input_list_struct;
my @gate_queue;
#my @fanout_test;
my $num_inputs=0;
my $num_outputs=0;
my $num_wires=0;
my $num_gates=0;
my $gate_name_temp;
my $gate;
my $line;
my $role;
my $inp;
my $inp_test;
#Test netlist file
if($bench_file =~ /(.*).v/)
{
$file_name = $1;
}
else
{
print "Format of bench file name: circuit_name.v \n example : s1423.v\n";
}
#Read Netlist File
while(<>)
{
my $INPUT_DATA = $_;
chomp($INPUT_DATA);
{
#MODULE NAME
if($INPUT_DATA =~ /module (.*) (.*);/)
{
$circuit_name = $1;
print "circuit name = $circuit_name\n";
}
#INPUT OUTPUT WIRES
if($INPUT_DATA =~ /input (.*);/)
{
@input_array = split /,/, $1;
}
if($INPUT_DATA =~ /output (.*);/)
{
@output_array = split /,/, $1;
}
if($INPUT_DATA =~ /wire (.*);/)
{
@wire_array = split /,/, $1;
}
my @wire1;
my @wire2;
my @wire3;
my $gate_name_temp;
my $gate;
my $line;
my $role;
#AND, OR, NAND, NOR, XOR
if($INPUT_DATA =~ /(.*) (.*) \(\.Y\((.*)\),\.A\((.*)\),\.B\((.*)\)\);/)
{
push @gates,
{
num_inputs => 2,
gate_type => "$1",
gate_name => "$2",
output =>
{
wire_name => "$3",
sa0 => 1,
sa1 => 1,
level => 0,
},
input_1 =>
{
wire_name => "$2_$4",
sa0 => 1,
sa1 => 1,
level => 0,
},
input_2 =>
{
wire_name => "$2_$5",
sa0 => 1,
sa1 => 1,
level => 0,
},
processed => 0,
processed_ip1 => 0,
processed_ip2 => 0,
gate_level => -1,
shifted => 0
};
}
#INV, BUF
#DE - Doesnt Exist
#renaming the gates at inputs of the gates for fanouts
if($INPUT_DATA =~ /(INVX1|BUFX1) (.*) \(\.Y\((.*)\),\.A\((.*)\)\);$/)
{
$gate_name_temp = $2;
push @gates,
{
num_inputs => 1,
gate_type => "$1",
gate_name => "$2",
output =>
{
wire_name => "$3",
sa0 => 1,
sa1 => 1,
level => 0,
},
input_1 =>
{
wire_name => "$2_$4",
sa0 => 1,
sa1 => 1,
level => 0,
},
processed => 0,
processed_ip1 => 0,
gate_level => -1,
shifted => 0
};
}
}
}
#File Read complete
#wire struct holds fault data for all wires
#input_list_struct is used for levelization
for $element (@input_array){
print "input: $element\n";
push @wire_struct, { wire_name => "$element", sa0 => 1, sa1 =>1, level => 0};
push @input_list_struct, {wire_name => "$element", sa0 => 1, sa1 => 1, level => 0};
}
for $element (@wire_array){
push @wire_struct, { wire_name => "$element", sa0 => 1, sa1 =>1, level => -1};
}
for $element (@output_array){
push @wire_struct, { wire_name => "$element", sa0 => 1, sa1 =>1, level => -1};
}
print "Initial inputs\n";
for my $href ( @input_list_struct ) {
print "{ ";
for my $role ( keys %$href ) {
print "$role=$href->{$role} ";
}
print "}\n";
}
$num_gates = scalar @gates;
my $index=0;
#gate_processed = 2 then all inputs are processed
#shift gate into the queue if even one of the inputs processed
while($num_gates != 0)
{
for my $gate(@gates){
for my $inp (@input_list_struct){
my $inp_test = $inp->{wire_name};
if(($gate->{input_1})->{wire_name} =~ m/$inp_test$/){
$gate->{processed_ip1} = 1;
if($gate->{num_inputs}==1){
print "NOTE: $gate->{gate_name}:$gate->{processed}\n";
getc();
if($gate->{processed}!=$gate->{num_inputs}){
unshift(@gate_queue,$gate);
}
}
elsif($gate->{processed_ip2}==1){
$gate->{processed}=$gate->{num_inputs};
}
elsif($gate->{processed}!=$gate->{num_inputs}){
if($gate->{shifted}==0){
print "1. shifting $gate->{gate_name} to gate queue\n";
getc();
unshift(@gate_queue,$gate);
}
}
}
if(($gate->{num_inputs}!=1)){
if(($gate->{input_2})->{wire_name} =~ m/$inp_test$/){
$gate->{processed_ip2} = 1;
if($gate->{processed_ip1}==1){
$gate->{processed}=$gate->{num_inputs};
}
if($gate->{processed}!=$gate->{num_inputs}){
if($gate->{shifted}==0){
print "2. shifting $gate->{gate_name} to gate queue\n";
getc();
unshift(@gate_queue,$gate);
}
}
}
}
}
}
print "Gates in gate queue\n";
for my $line (@gate_queue)
{
for my $role (keys %$line)
{
if($role =~ m/^input_1$/)
{
print "$role: $line->{$role}->{wire_name},";
print "lvl: $line->{$role}->{level},";
}
elsif($role =~ m/^input_2$/)
{
print "$role: $line->{$role}->{wire_name},";
print "lvl: $line->{$role}->{level},";
}
elsif($role =~ m/^output$/)
{
print "$role: $line->{$role}->{wire_name},";
print "lvl: $line->{$role}->{level},";
}
else
{
print "$role:$line->{$role},";
}
}
print "\n";
}
getc();
#if both inputs of the gates are processed, then calculate the level of the gate
#if only one of the inputs are processed, then add the gate to the end
my $num_gate_queue = scalar @gate_queue;
while ($num_gate_queue != 0)
{
$gate = pop(@gate_queue);
if($gate->{num_inputs}==1){
print "Number of gates in queue: $num_gate_queue";
if($gate->{processed_ip1}==1){
$gate->{processed}=$gate->{num_inputs};
}
}
if($gate->{processed}==$gate->{num_inputs}){
if($gate->{num_inputs}==2){
if(($gate->{input_1}->{level})>($gate->{input_2}->{level})){
$gate->{gate_level} = ($gate->{input_1}->{level});
}
else{
$gate->{gate_level} = ($gate->{input_2}->{level});
}
$gate->{gate_level}++;
$gate->{output}->{level}=$gate->{gate_level};
unshift(@input_list_struct,$gate->{output});
$num_gate_queue--;
$num_gates--;
print "Number of gates left $num_gates";
getc();
}
elsif($gate->{num_inputs}==1){
print "input level: $gate->{input_1}->{level}\n";
getc();
$gate->{gate_level} = $gate->{input_1}->{level};
$gate->{gate_level}++;
$gate->{output}->{level}=$gate->{gate_level};
print "$gate->{gate_name}: $gate->{gate_level}";
unshift(@input_list_struct,$gate->{output});
$num_gate_queue--;
$num_gates--;
print "Number of gates left $num_gates";
getc();
}
}
else{
# if($gate->{shifted}==0){
print "3. shifting $gate->{gate_name} to gate queue\n";
getc();
unshift(@gate_queue,$gate);
$num_gate_queue--;
#gates that are not processed because of lack of second input being processed are shifted in here, they need not be shifted again
$gate->{shifted}=1;
# }
}
}
print "updated input list\n";
for my $href ( @input_list_struct ) {
print "{ ";
for my $role ( keys %$href ) {
print "$role=$href->{$role} ";
}
print "}\n";
}
#the updated levels of the wires are present in input_list_struct
#update the fanouts of the gate with the levels from this struct
print "modifying gate: level input of gate\n";
for $gate(@gates){
for $inp (@input_list_struct){
$inp_test = $inp->{wire_name};
if(($gate->{input_1})->{wire_name} =~ m/$inp_test$/){
$gate->{input_1}->{level} = $inp->{level};
print "$gate->{gate_name}: $gate->{input_1}->{wire_name} - $gate->{input_1}->{level}\n";
}
if($gate->{num_inputs}!=1){
if(($gate->{input_2})->{wire_name} =~ m/$inp_test$/){
$gate->{input_2}->{level} = $inp->{level};
}
}
}
}
}
print "gate: level\n";
for $gate (@gates){
print "$gate->{gate_name}: $gate->{gate_level}\n";
}
</code></pre>
<br />
<br />
</div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-17413871647474021612012-10-30T23:43:00.004-07:002012-10-30T23:48:48.804-07:00The shot never fired<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<br />
<span style="font-family: Verdana,sans-serif;"><br />"I will go to paradise" he thought. Sitting there with the gun in his pocket in the jeep. He was waiting. "When do they come?" his friend asked. "4:30" he said keeping his mind focused on the task he had been given. "I will go to paradise and I will be under the feet of the almighty. I will be freed from my sins since I am doing this for him." he thought. "but....". <br /><br />He had long stopped listening to the tiny squeeky voice inside his head. Whenever he was on a mission dictated to him by god, the voice was there. A voice at a pitch slightly higher than his voice. The voice always questioned him. It always started with a but. He had learnt to control it. He was taught to not listen to the voice. "It is the devil" they told him when he was all but 14. "If you listen to the voice, you will be condemned for all eternity to hell. you will be burning in brimstone. You will know only pain and suffering". His tiny mind was acting on its instincts. It trusted the bigger man and took him for granted. He learnt to not trust the voice. He learnt to not trust himself. <br /><br />The task at hand confused him but he dared not question the intentions of god and those who entrusted him with the task. He was but chosen, he was but blessed. How can he be confused? He kept reminding it to himself. He also became aware that the voice was becoming louder. "But..". <br /><br />His thought shifted, his focus waned as a flood of memories rushed. Aisha, his little sister, playing with a ragged doll. She seemed very happy and without a care in the world. The moment she was born, he knew it was his mission to care for her and protect her. Her smile evoked the deepest feelings of tenderness in him. He sat beside her for hours answering all her curious questions, watching her jump from one object of interest to another. He felt his heart light with love when thinking about how she used to wait for him everyday near the door of their beautiful home. He saw her bloom into a beautiful flower in front of his eyes. He showered her with gifts when he himself dressed like a pauper. "STOP" she used to scream. "Dont keep doing this. Please listen to me" she said. He never did. He missed her. Sadly the unrelenting train of thought, mercilessly lead him through the course of events. It did not spare him and be satisfied with just the happy days in his life. His eyes darkened. His heart grew heavy like a cloth filled with tears. A rage grew in his heart, burning fiery blue, consuming his blood for fuel. He remembered the drones. <br /><br />"She will be avenged. They will pay." he thought. His friend suddenly called out to him, shaking him out of the haze. "Here they come, be ready quick". He felt he had the vision of an eagle. He felt nothing in the world would stop him. They ambushed the school van. "Come Out" he commanded. A train of little girls came out, crying in fear. He had his gun out and pointed at them. "They are small kids. Do not harm them" the school van driver pleaded. He knew whom he had to shoot, he knew who was conspiring with the enemy, he knew who is going to bring him closer to god. He aimed the gun for her neck. All of a sudden there was a high pitched scream from inside him. "STOP", He could recoginse it. "Dont keep doing this. Please listen to me" it pleaded. He heard a soulful cry, his ears shattered, breathing stopped and brains burned. Tears rained from his eyes uncontrollably. "I will listen to you my dear sister. I will always listen to you." He pointed the gun to his head. The cry seized to be heard to him anymore. He felt nothing of the pain or the agony. It did not feel like burning in brimstone. He felt peace as his body fell. His head never hit the ground. He felt joy. He felt Aisha's lap.</span></div>
</div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-3321318971658268442012-10-30T13:47:00.001-07:002012-10-30T13:49:45.365-07:00OpenSPARC Synthesis using Design Compiler<div style="text-align: justify;">
<span style="font-size: small;">OpenSPARCT1 comes with a built in script called rsyn that is used to synthesize the required verilog files using synopsys design compiler. All the modules are individually compiled (except the mega cells) and you get the flattened and hierarchical verilog netlist file for individual modules. You do not have the netlist file for the entire OpenSPARCT1 yet and that has to be done manually. <br /><br /><b> </b></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><b>Important Scripts provided by SUN </b></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><br />The OpenSPARCT1/design/sys/synopsys/script folder contains the scripts to configure and run synopsys <br /> </span></div>
<div style="text-align: justify;">
<span style="font-size: small;">There are two configuration files <br /> 1. io configuration - project_io_cfg.scr <br /> 2. sparc configuration - project_sparc_cfg.scr </span></div>
<div style="text-align: justify;">
<span style="font-size: small;">they contain the configuration information. <br /><br /><b>Rsyn flow </b><br />The rsyn command calls identifies the tool that is to be used and then calls the "rsyn,1.0" file in OpenSPARCT1/tools/perlmod <br /><br />1. The rsyn file reads the block list that is present in OpenSPARCT1/design/sys/synopsys/. <br />2. It runs the synthesis for each block and stores the synthesized files in /design/sys/iop/$block/synopsys folder for each block <br />3. To do this it calls the run.scr file <br />This synthesizes all the files in the block list.</span></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<span style="font-size: small;">Here I describe different processes. If you feel the method is not right and changes are to be done. kindly let me know. </span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><br /></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><a href="http://abishekramdas.blogspot.com/2012/10/synthesizing-individual-modules-of.html">Synthesizing Individual modules using rsyn</a></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><a href="http://abishekramdas.blogspot.com/2012/10/synthesizing-entire-opensparct1.html">Synthesizing the entire processor using design-vision</a></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><a href="http://abishekramdas.blogspot.com/2012/10/synthesizing-just-sparc-core-using.html">Synthesizing the SPARC Core alone using design-vision</a></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><a href="http://abishekramdas.blogspot.com/2012/10/synthesizing-individual-blocks.html">Synthesizing individual blocks of the SPARC Core using design-vision</a></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><a href="http://abishekramdas.blogspot.com/2012/10/appendix.html">Appendix</a></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><br /></span></div>
<div style="text-align: justify;">
<span style="font-size: small;">Have fun,</span></div>
<div style="text-align: justify;">
<span style="font-size: small;">Abishek</span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-11487019857739855722012-10-30T13:45:00.001-07:002012-10-30T13:45:21.721-07:00Synthesizing individual blocks separately
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<div style="margin-bottom: 0in; page-break-before: always;">
<span style="font-family: Verdana, sans-serif; font-size: small;">It would be required to synthesize individual blocks in SPARC separately. For example, the method to synthesize the Load Store Unit is described here.</span><span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; page-break-before: always;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">You
need to have successfully run rsyn -<a href="http://abishekramdas.blogspot.com/2012/10/synthesizing-individual-modules-of.html">how?</a></span></span></div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">example
lsu unit present in design/sys/iop/sparc/lsu </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"><b>Steps
</b></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">1.
Create a work folder anywhere you like </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">2.
cd into design/sys/iop/sparc/lsu </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">3.
Use the following script to collect the flat_files from the location </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">4.
Use the following script to extract the flat nestlist from all
modules inside lsu to a folder called flat_files </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> Script:
file_collect.sh (location /design/sys/iop/sparc/lsu) </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> cd
/home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> for
FILE in $(find . -type f | grep -e "flat") </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> do
</span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">
echo "cp ${FILE}
/home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu/flat_files"
</span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">
cp ${FILE}
/home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu/flat_files </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> done
</span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">5.
copy the files that are present in the flat_files folder to the work
folder. </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">6.
Copy the top file for the lsu namely lsu.v present in
design/sys/iop/sparc/lsu/rtl to the work folder </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">6.
Invoke design vision, run the <a href="http://abishekramdas.blogspot.com/2012/10/appendix.html">configuration script</a> to set up
the libraries and work folders etc </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">7.
File -> analyze, add all the files that are present in the work
directory </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">8.
File -> Elaborate, you will get warnings saying that sram modules
(bw_r*) are missing, they cannot be synthesized because they are
memory modules </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">9.
Design -> compile </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">10.
Command "report_qor > result_file" to report the area
gate information etc. </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">11.
Save the synthesized file. File -> save</span></span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-56906941157772459052012-10-30T13:41:00.001-07:002012-10-30T13:41:06.220-07:00List of file to compile just the SPARC core
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<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;"><b>List
of files to compile sparc core in design vision present in
design/sys/iop/sparc/flat_files </b></span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<br />
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">bw_clk_cl_sparc_cmp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_stb_rwctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ffu_ctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_invctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">spu_lsurpt_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">cpx_spc_buf_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_stb_rwdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ffu_dp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_mbist_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">spu_madp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">cpx_spc_rpt_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_tagdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ffu.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_sscan_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">spu.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_dcdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_tlbdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ffu_vis_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_swl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu_hyperv_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_dctldp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_dcl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu_incr64_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_dctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_exu_alu_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_dec_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_wseldp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu_misctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_excpctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_exu_byp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_errctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_mul_top_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu_mmu_ctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_qctl1_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_exu_div_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_errdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_tlu_intctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu_mmu_dp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_qctl2_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_exu_ecc_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_fcl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_tlu_intdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu_pib_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_qdp1_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_exu_ecl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_fdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu_tcl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_qdp2_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_exu_rml_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_ifqctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">spc_pcx_buf_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu_tdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_stb_ctldp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_exu_shft_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_ifqdp_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">spu_ctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">tlu.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">lsu_stb_ctl_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_exu.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">sparc_ifu_imd_flat.v
</span></span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">spu_lsurpt1_flat.v</span></span></span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-52605282366949227702012-10-30T13:40:00.001-07:002012-10-30T13:46:00.941-07:00Synthesizing just the SPARC Core using design-vision<style type="text/css">
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<br />
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span></div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">You
need to have successfully run rsyn - <a href="http://abishekramdas.blogspot.com/2012/10/synthesizing-individual-modules-of.html">how?</a></span></span></div>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Sparc
has a number of blocks. </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">bw_clk_cl_sparc_cmp
cpx_spc_buf cpx_spc_rpt exu ffu ifu lsu mul spu tlu
spc_pcx_buf </span></span></div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Steps
are </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">1.
collect all the flattened netlist files from each block in work
folder </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">file_collect.sh
- location design/sys/iop/sparc </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> cd
/home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/ </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> for
FILE in $(find . -type f | grep -e "flat") </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> do
</span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">
echo "cp ${FILE}
/home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files" </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">
cp ${FILE}
/home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> done
</span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">cd
design/sys/iop/sparc </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">mkdir
flat_files </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">./file_collect.sh
</span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">All
the flat files in the sparc folder are present in
/design/sys/iop/sparc/flat_files </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">2.
collect the top level files from each of the blocks </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> you
will find the top level blocks for each module in the rtl folder
inside that module </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">current
fldr - design/sys/iop/sparc/ </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">1.
sparc_ffu.v - ffu/rtl </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">2.
sparc_ifu.v - ifu/rtl </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">3.
sparc_exu.v - exu/rtl </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">4.
lsu.v - lsu/rtl </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">5.
tlu.v - tlu/rtl </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">6.
spu.v - spu/rtl </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">7.
sparc.v - ./rt/ </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">copy
these files into flat_files mentioned above. </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Now
all the required files are in flat_files folder. </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<a href="http://abishekramdas.blogspot.com/2012/10/list-of-file-to-compile-just-sparc-core.html"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">List of Files</span></span></a></div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">1.
Invoke design vision, run the <a href="http://abishekramdas.blogspot.com/2012/10/appendix.html">configuration script</a> to set up the
libraries and work folders etc </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">2.
File -> analyze, add all the files that are present in the work
directory </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">3.
File -> Elaborate, you will get warnings saying that sram modules
(bw_r*) are missing, they cannot be synthesized because they are
memory modules </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">4.
Design -> compile </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">5.
Command "report_qor > result_file" to report the area
gate information etc. </span></span>
</div>
<div style="font-weight: normal; margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">6.
Save the synthesized file. File -> save</span></span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-8361220069521406922012-10-30T13:35:00.000-07:002012-10-30T13:36:53.722-07:00Synthesizing the entire OpenSPARCT1 processor using design-vision (design compiler)<div style="text-align: justify;">
<style type="text/css">
<!--
@page { margin: 0.79in }
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</style>
</div>
<br />
<div style="margin-bottom: 0in; page-break-before: always; text-align: justify;">
<span style="font-size: small;"><br /></span></div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">If
we are required to find area information or the routing information
of the entire processor (with all 8 cores etc) we have to manually
compile the flattened netlist file with the top level file of the
processor. The procedure is described here. </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">The
top level module for OpenSPARCT1 is “iop.v” located at
design/sys/iop/rtl</span></span></div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"><b>Synthesize
the whole processor using design vision </b></span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"><b>I
need the area information of the processor with all 8 cores </b></span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">1.
Run rsyn to generate all the flattened netlist - <a href="http://abishekramdas.blogspot.com/2012/10/synthesizing-individual-modules-of.html">how?</a></span></span></div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">2.
collect all the flattened netlist file in a folder </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> File:
file_collect.sh </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> Location
~/opt/OpenSPARCT1/flat_files </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> cd
/home/ar2654/opt/OpenSPARCT1/design/sys/iop </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> for
FILE in $(find . -type f | grep -e "flat") </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> do
</span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">
echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files"
</span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">
cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> done
</span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">3.
The top level file for the entire OpenSPARC chip is present in
design/sys/iop/rtl and is called iop.v. </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> The
processors and their connections are instantiated in this file. </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> This
file does not instantiate the processors or other modules because of
"ifdef" conditions (look inside iop.v) </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> We
need to define our requirements (number of processors required, other
hardware required) and I defined them in iop.h
(design/sys/iop/include) </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> For
example to instantiate all 8 SPARC cores, we need to add the
following lines in iop.h </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> `define
RTL_SPARC0 1 </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> `define
RTL_SPARC1 1 </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> .
</span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> .
</span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> .
</span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> `define
RTL_SPARC7 1 </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> Other
ifdef conditions are present in iop.v. In my case I defined
everything to be 1. </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> alternatively
you can remove the ifdef conditions in iop.v </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">4.
This modified top level file (iop.v) file is added to the flat_files
folder </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">5.
design_vision is started inside a working directory, </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">6.
The configuration synopsys_dc.setup script is run – <a href="http://abishekramdas.blogspot.com/2012/10/appendix.html">sample dc_script file</a> </span></span></div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">7.
Analyze all the files that are there in the flat_files folder (File
-> Analyze) </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">8.
Elaobrate the design with OpenSPARCT1 as the top module. (File ->
Elaborate) </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> If
there are unresolved references other than the memory modules
(bw_r*), find those modules and add them to the flat_files folder. </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> Analyze
the unresolved references and elaborate until references to memory
modules only remain </span></span>
</div>
<div style="margin-bottom: 0in; text-align: justify;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">9.
Compile Design to generate the area information</span></span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-50743989860852216842012-10-30T13:34:00.000-07:002012-10-30T13:34:15.680-07:00Appendix
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<br />
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;"><b>Configuration
file for design_vision </b></span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">#
synopsys_dc.setup file for opensparc </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<br />
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">#
Define the lsi_10k library </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">set
SYN_LIBS /opt/synopsys/syn/libraries/syn </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">set
SPARC_INC /home/ar2654/opt/OpenSPARCT1/design/sys/iop/include </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<br />
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">#
Define the libraries and search path </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">set
search_path [concat $search_path ${SYN_LIBS} ${SPARC_INC}] </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">set
target_library ${SYN_LIBS}/lsi_10k.db </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">set
link_library [concat "*" $target_library] </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">set
symbol_library ${SYN_LIBS}/lsi_10k.sdb </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<br />
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">define_design_lib
WORK -path home/ar2654/opt/OpenSPARCT1/SYN_full/WORKar2654@nanovlsi %
</span></span></span>
</div>
<div style="margin-bottom: 0in;">
<br />
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;"><b>File:
file_collect.sh </b></span></span></span>
</div>
<div style="margin-bottom: 0in;">
<br />
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">cd
/home/ar2654/opt/OpenSPARCT1/design/sys/iop </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">for
FILE in $(find . -type f | grep -e "flat") </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">do
</span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"> <span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">echo
"cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files" </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"> <span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">cp
${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files </span></span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black;"><span style="font-family: Verdana, sans-serif;"><span style="font-size: x-small;">done
</span></span></span>
</div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-31861350835202295582012-10-30T13:29:00.002-07:002012-10-30T13:29:21.656-07:00Synthesizing the individual modules of OpensparcT1 - RSYN
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<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">rsyn
compiles all the files using design compiler. The default library
used is <b>lsi_10k.db</b></span></span><br />
<ol>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Open
Design and verification guide </span></span>
</li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">In
the quick start section 1.3.1 follow unzip and untar commands </span></span>
</li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">cd
to the folder untared </span></span>
</li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Open
the OpenSPARC.cshrc script </span></span>
</li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Edit
the document to set up the environment for <a href="http://abishekramdas.blogspot.com/2012/10/sample-opensparct1cshrc.html">openSPARC.cshrc</a> </span></span></li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> synopsys
libraries - /opt/synopsys/syn </span></span>
</li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;"> sparcos5
libraries - </span></span>
</li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">I
was not able to find the libraries at the place mentioned in the
document so I used to locate command to locate sparcos5 libraries </span></span>
</li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">locate
sparcOS5 </span></span>
</li>
<li><span style="color: black; font-size: small;"> <span style="font-family: Verdana, sans-serif;">source
the .tcshrc_synopsys file (it contains the license file in my case)</span></span></li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">source
OpenSPARCT1.cshrc file </span></span>
</li>
<li><span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">rsyn
-all</span></span></li>
</ol>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">If
everything runs well you can find</span></span></div>
<ol>
<li><div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">In
the folder of every component (analog/*, ccx/* etc) you can find a
folder called synopsys</span></span></div>
</li>
<li><div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Inside
that folder you will have log files for commands and design compiler</span></span></div>
</li>
<li><div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">A
gate folder which contains the compiled, flattened and hierarchical
netlist</span></span></div>
</li>
<li><div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">A
log folder which contains the area report for that cell</span></span></div>
</li>
</ol>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-family: Verdana, sans-serif; font-size: small;"><b>ERRORS</b></span><span style="font-size: small;">:</span></div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Runs
well till the module ctu is being synthesized </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Abort
at 51 </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Fatal:
Internal system error, cannot recover. </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Googled
this error and found </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><a href="https://forums.oracle.com/forums/thread.jspa?threadID=2122695&tstart=0&messageID=9110858"><span style="color: black;"><span style="font-family: Verdana, sans-serif;">Abort at 51 error - solved</span></span></a></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">He
says </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;">“<span style="font-family: Verdana, sans-serif;">I
sorted this error it has to do with the fact that the read_file
function in DC "Cannot pass parameters (must use directives in
HDL)" as documented in table 6-2 of this pdf file
http://www.vlsiip.com/dc_shell/dcug_6.pdf this means that the scripts
for JBI and CTU must be edited. So with the CTU module the file
ctu_revision.v has to be excluded from the "rtl_files" list
at the top of the user_cfg.scr script (found in...
/design/sys/iop/ctu/synopsys/script directory) and the following
lines added at the bottom of the script: </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">read_file
-format verilog -define RUNDC
$dv_root/design/sys/iop/ctu/rtl/ctu_jtag_id.v </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">analyze
-format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_jtag_id.v </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">elaborate
ctu_jtag_id </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">read_file
-format verilog -define RUNDC
$dv_root/design/sys/iop/ctu/rtl/ctu_mask_id.v </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">analyze
-format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_mask_id.v </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">elaborate
ctu_mask_id </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">read_file
-format verilog -define RUNDC
$dv_root/design/sys/iop/ctu/rtl/ctu_revision.v </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">analyze
-format verilog $dv_root/design/sys/iop/ctu/rtl/ctu_revision.v </span></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">elaborate
ctu_revision ”</span></span></div>
<div style="margin-bottom: 0in;">
<span style="font-size: small;"><br /></span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Works
you need to do the same for more than one file . The files that fail
need to be analyzed and elaborated. See appendix for sample
user_cfg.scr file for ctu.</span></span></div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"> </span>
</div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Everytime
it fails, I go to the filename.log file in
/design/sys/iop/ctu/synopsys and look at the last file that is
executed. I then remove that line form the script file and added it
at the end of the script in the format mentioned above.</span></span></div>
<div style="margin-bottom: 0in;">
<br /></div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Have fun,</span></span></div>
<div style="margin-bottom: 0in;">
<span style="color: black; font-size: small;"><span style="font-family: Verdana, sans-serif;">Abishek </span></span></div>
Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-27618686042138990522012-10-30T13:27:00.001-07:002012-10-30T13:27:37.390-07:00Sample OpenSPARCT1.cshrc<br />
# User needs to define these new variables<br />
setenv DV_ROOT /home/location_to/OpenSPARCT1<br />
setenv MODEL_DIR /home/location_to/OpenSPARCT1_model<br />
<br />
if (`uname -s` == "SunOS") then<br />
setenv CC_BIN "/usr/dist/pkgs/sunstudio_`uname -p`/SUNWspro/bin"<br />
else<br />
setenv CC_BIN /usr/bin<br />
endif<br />
<br />
# Please define VERA_HOME only if you have VERA, otherwise comment it out.<br />
if ((`uname -s` == "SunOS") && (`uname -p` == "sparc")) then<br />
# setenv VERA_HOME /import/EDAtools/vera/vera,v6.2.10/5.x<br />
else<br />
# setenv VERA_HOME<br />
endif<br />
<br />
# Please define VCS_HOME only if you have VCS, otherwise comment it out.<br />
#setenv VCS_HOME /import/EDAtools/vcs/vcs7.1.1R21<br />
<br />
# Please define NCV_HOME only if you have NC-Verilog, otherwise comment it out.<br />
#setenv NCV_HOME /import/EDAtools/ncverilog/ncverilog.v5.3.s2/5.x<br />
<br />
# Please define NOVAS_HOME only if you have Debussy, otherwise comment it out.<br />
if ((`uname -s` == "SunOS") && (`uname -p` == "sparc")) then<br />
# setenv NOVAS_HOME /import/EDAtools/debussy/debussy,v5.3v19/5.x<br />
endif<br />
<br />
# Please define SYN_HOME only if you are running synopsys<br />
setenv SYN_HOME "/opt/synopsys/syn"<br />
<br />
# Please define SYNP_HOME only if you are running Synplicity<br />
#setenv SYNP_HOME "/import/EDAtools/synplicity/synplify.v8.6.1/fpga_861"<br />
#setenv LM_LICENSE_FILE<br />
"/import/EDAtools/licenses/synopsys_key:/import/EDAtools/licenses/ncverilog_key"<br />
<br />
# New variables (fixed or based on $DV_ROOT)<br />
setenv TRE_ENTRY /<br />
setenv TRE_LOG nobody<br />
setenv TRE_SEARCH "$DV_ROOT/tools/env/tools.iver"<br />
setenv ENVDIR $DV_ROOT/tools/env<br />
setenv PERL_MODULE_BASE $DV_ROOT/tools/perlmod<br />
<br />
# Synopsys variables from $SYN_HOME<br />
setenv SYN_LIB /opt/synopsys/syn/libraries/syn<br />
setenv SYN_BIN /opt/cadence/local/vtvtlib25/Synopsys_Libraries/vtvtlib25/sparcOS5<br />
<br />
# Set Perl related variables<br />
if ((`uname -s` == "SunOS") && (`uname -p` == "sparc")) then<br />
setenv PERL_VER 5.8.7<br />
setenv PERL_PATH $DV_ROOT/tools/perl-$PERL_VER<br />
setenv PERL5_PATH $DV_ROOT/tools/perl-$PERL_VER/lib/perl5<br />
setenv PERL_CMD "$PERL_PATH/bin/perl"<br />
setenv PERL5LIB $PERL5_PATH<br />
else<br />
setenv PERL_CMD "/usr/bin/perl"<br />
endif<br />
<br />
# Set path<br />
setenv PATH ".:$DV_ROOT/tools/bin:$SYN_BIN/:$CC_BIN/:$PATH"<br />
set path = (. $DV_ROOT/tools/bin $SYN_BIN $CC_BIN $path)Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-29618751734340346992012-10-17T18:25:00.001-07:002012-10-17T18:27:50.730-07:00Equivalent Fault CollapsingHere is an equivalent fault collapsing program, The aim is to read a combinational Verilog netlist file and perform equivalent fault collapsing for the circuit.<br />
<br />
The program does equivalent fault collapsing for the following gate types<br />Two-input, one-output gates or One-input, one-output gates as follows:<br />AND2X1<br />OR2X1<br />NAND2X1<br />NOR2X1<br />XOR2X1<br />INVX1<br />BUFX1<br /><br />Upgrade: Fanouts need to be considered separately. upgrade the program to include fanouts also
<pre style="font-family:arial;font-size:12px;border:1px dashed #CCCCCC;width:99%;height:auto;overflow:auto;background:#f0f0f0;;background-image:URL(http://2.bp.blogspot.com/_z5ltvMQPaa8/SjJXr_U2YBI/AAAAAAAAAAM/46OqEP32CJ8/s320/codebg.gif);padding:0px;color:#000000;text-align:left;line-height:20px;"><code style="color:#000000;word-wrap:normal;"> #!/usr/bin/perl
#fault_collapsing.plx
use warnings;
use strict;
my $bench_file = $ARGV[0];
my $file_name;
my $circuit_name;
my $element;
my @input_array;
my @output_array;
my @wire_array;
my @gates;
my @sorted_gates;
my @wire_struct;
#my @fanout_test;
my $num_inputs=0;
my $num_outputs=0;
my $num_wires=0;
my $num_gates=0;
#Test netlist file
if($bench_file =~ /(.*).v/)
{
$file_name = $1;
}
else
{
print "Format of bench file name: circuit_name.v \n example : s1423.v\n";
}
#Read Netlist File
while(<>)
{
my $INPUT_DATA = $_;
chomp($INPUT_DATA);
{
#MODULE NAME
if($INPUT_DATA =~ /module (.*) (.*);/)
{
$circuit_name = $1;
print "circuit name = $circuit_name\n";
}
#INPUT OUTPUT WIRES
if($INPUT_DATA =~ /input (.*);/)
{
@input_array = split /,/, $1;
}
if($INPUT_DATA =~ /output (.*);/)
{
@output_array = split /,/, $1;
}
if($INPUT_DATA =~ /wire (.*);/)
{
@wire_array = split /,/, $1;
}
#AND, OR, NAND, NOR, XOR
if($INPUT_DATA =~ /(.*) (.*) \(\.Y\((.*)\),\.A\((.*)\),\.B\((.*)\)\);/)
{
push @gates, { gate_type => "$1", gate_name => "$2", output => "$3", input_1 => "$4", input_2 => "$5", processed => 0};
}
#INV, BUF
#DE - Doesnt Exist
if($INPUT_DATA =~ /(INVX1|BUFX1) (.*) \(\.Y\((.*)\),\.A\((.*)\)\);$/)
{
push @gates, { gate_type => "$1", gate_name => "$2", output => "$3", input_1 => "$4", input_2 => "DE", processed => 0};
}
}
}
#File Read complete
#wire struct holds fault data for all wires
for $element (@input_array){
print "input: $element\n";
push @wire_struct, { wire_name => "$element", sa0 => 1, sa1 =>1};
}
for $element (@wire_array){
push @wire_struct, { wire_name => "$element", sa0 => 1, sa1 =>1};
}
for $element (@output_array){
push @wire_struct, { wire_name => "$element", sa0 => 1, sa1 =>1};
}
=pod
print "\n";
for my $href ( @wire_struct ) {
print "{ ";
for my $role ( keys %$href ) {
print "$role=$href->{$role} ";
}
print "}\n";
}
=cut
$num_gates = scalar @gates;
my $index=0;
my @remd_gates_outputs;
my $gate_processed_flag=0;
while($num_gates>0)
{
$gate_processed_flag=0;
print "Number of Gates = $num_gates";
for my $gate (@gates)
{
print "\ngate fetched: $gate->{gate_name}";
if($gate->{processed}==0)
{
print "\ngate under process: $gate->{gate_name}";
#see if any of the inputs map to a single input gate
if($gate->{input_2}=~ m/^DE$/)
{
print "\nsingle input";
print "\ngate input : $gate->{input_1}";
for my $inp (@input_array)
{
if($gate->{input_1} =~ m/^$inp$/)
{
print "inp matches";
#for 1 input gate
print "\n";
for my $role ( keys %$gate )
{
print "$role=$gate->{$role} ";
}
#NOT GATES
if($gate->{gate_type} =~ m/^INVX1$/)
{
for my $wire (@wire_struct)
{
if($wire->{wire_name} =~ m/^$inp$/)
{
$wire->{sa0} = 0;
$wire->{sa1} = 0;
print "\n changing $inp sa0 to 0 and sa1 to 0";
}
}
$gate->{processed}=1;
$num_gates--;
push @remd_gates_outputs, $gate->{output};
$gate_processed_flag=1;
}
#BUFFER GATES
if($gate->{gate_type} =~ m/^BUFX1$/)
{
for my $wire (@wire_struct)
{
if($wire->{wire_name} =~ m/^$inp$/)
{
$wire->{sa0} = 0;
$wire->{sa1} = 0;
print "\n changing $inp sa0 to 0 and sa1 to 0";
}
}
$gate->{processed}=1;
$num_gates--;
push @remd_gates_outputs, $gate->{output};
$gate_processed_flag=1;
}
}
}
}
for my $input1 (@input_array)
{
if($gate->{processed}==0)
{
print "\nInput wire 1: $input1";
if($gate->{input_1} =~ m/^$input1$/)
{
print "\t$gate->{gate_name}\t";
for my $input2 (@input_array)
{
print "\nInput wire 2: $input2";
#for two input gates
if($gate->{input_2} =~ m/^$input2$/)
{
print "Gate under consideration: $gate->{gate_name}";
print "\n";
for my $role ( keys %$gate )
{
print "$role=$gate->{$role} ";
}
#NAND GATES
if($gate->{gate_type} =~ m/^NAND2X1$/)
{
for my $wire (@wire_struct)
{
if($wire->{wire_name} =~ m/^$input1$/)
{
$wire->{sa0} = 0;
print "\n changing $input1 sa0 to 0";
}
if($wire->{wire_name} =~ m/^$input2$/)
{
$wire->{sa0} = 0;
print "\n changing $input2 sa0 to 0";
}
}
$gate->{processed}=1;
$num_gates--;
push @remd_gates_outputs, $gate->{output};
$gate_processed_flag=1;
}
#AND GATES
if($gate->{gate_type} =~ m/^AND2X1$/)
{
print "\nhi i am inside\n";
for my $wire (@wire_struct)
{
if($wire->{wire_name} =~ m/^$input1$/)
{
$wire->{sa0} = 0;
print "\n changing $input1 sa0 to 0";
}
if($wire->{wire_name} =~ m/^$input2$/)
{
$wire->{sa0} = 0;
print "\n changing $input2 sa0 to 0";
}
}
$gate->{processed}=1;
$num_gates--;
push @remd_gates_outputs, $gate->{output};
$gate_processed_flag=1;
}
#OR GATES
if($gate->{gate_type} =~ m/^OR2X1$/)
{
for my $wire (@wire_struct)
{
if($wire->{wire_name} =~ m/^$input1$/)
{
$wire->{sa1} = 0;
print "\n changing $input1 sa1to 0";
}
if($wire->{wire_name} =~ m/^$input2$/)
{
$wire->{sa1} = 0;
print "\n changing $input2 sa1 to 0";
}
}
$gate->{processed}=1;
$num_gates--;
push @remd_gates_outputs, $gate->{output};
$gate_processed_flag=1;
}
#NOR GATES
if($gate->{gate_type} =~ m/^NOR2X1$/)
{
for my $wire (@wire_struct)
{
if($wire->{wire_name} =~ m/^$input1$/)
{
$wire->{sa1} = 0;
print "\n changing $input1 sa0 to 0";
}
if($wire->{wire_name} =~ m/^$input2$/)
{
$wire->{sa1} = 0;
print "\n changing $input2 sa0 to 0";
}
}
$gate->{processed}=1;
$num_gates--;
push @remd_gates_outputs, $gate->{output};
$gate_processed_flag=1;
print "\nnum gates = $num_gates";
}
}
}
}
}
}
}
}
if($gate_processed_flag==1)
{
print "\ngate outputs to be made inputs\n";
for $element (@remd_gates_outputs)
{
print "$element\n";
push @input_array, $element;
}
print "\nThe list of gates after removed\n";
for $element (@gates)
{
if($element->{processed}==0){
print "$element->{gate_name}";}
}
print "Number of gates left: $num_gates";
}
my $x = ord(getc);
}
print "\n";
for my $href ( @wire_struct ) {
print "{ ";
for my $role ( keys %$href ) {
print "$role=$href->{$role} ";
}
print "}\n";
}
=pod
print "\n";
for my $href ( @gates ) {
print "{ ";
for my $role ( keys %$href ) {
print "$role=$href->{$role} ";
}
print "}\n";
}
=cut
=pod
my $href1;
for $href1 ( @gates ) {
for $element (@output_array){
if($href1->{output} =~ m/$element/){
print "output_arr=$element\n";
print "output=$href1->{output}\n ";
push @sorted_gates, $href1;
}
print "output_arr=$element\n";
print "output=$href1->{output}\n ";
}
}
=cut
=pod
print "\n";
for my $href ( @sorted_gates ) {
print "{ ";
for my $role ( keys %$href ) {
print "$role=$href->{$role} ";
}
print "}\n";
}
=cut
</code></pre>Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-31629820925939630492012-06-03T14:15:00.003-07:002012-06-03T14:21:56.938-07:00The answer that is known but still unknown.<div dir="ltr" style="text-align: left;" trbidi="on">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"> <span class="Apple-style-span" style="color: red;">"</span></span><span class="Apple-style-span" style="font-size: 12px;"><span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><span class="Apple-style-span" style="color: red;">No man can reveal to you aught but that which already lies half asleep in the dawning of your knowledge."</span></span></span><br />
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px; min-height: 14.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;">Whatever you have learnt is not new. It is already known to you. You are made aware of it by a teacher. It is human nature to know if told, to forget with time and then know again. Nevertheless we know it already. </span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px; min-height: 14.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;">It is the duty of the teacher to enlighten the student of what he already knows. The teacher cannot give his knowledge to the student but rather takes the student to what he knows by virtue of reasoning and coherent discussion. What the teacher actually gives the student is his love. </span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px; min-height: 14.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><span class="Apple-style-span" style="color: red;">"And even as each one of you stands alone in God's knowledge, so must each one of you be alone in his knowledge of God and in his understanding of the earth."</span></span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px; min-height: 14.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;">These are my interpretation of the words of Khalil Gibran. The clarity of his thought resonate truth in me. It seems true that whatever we understand we already know. So it is in us the answers to all questions. We have to find our way to it, a coherent way so that everything makes sense and all questions are answered. </span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px; min-height: 14.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;">I am trying to trace my thought process to the question of existence of god. There are a lot of things that are explained by science but extremely wonderful to be a mere coincidence. For example a calf that is born instinctively knows what to do. Similarly in the process of evolution, instinctively the female of a species chooses a male whose genes would be able to better protect her offsprings and help in the survival of species. How does it do it instinctively? Where do animals get their collective memory from. For example a pigeon need not have seen a falcon in its entire life but when it sees the silhouette of a falcon, it knows to fly away. Every species does something spectacular for their continuance. Where do all these memory come from? God maybe?</span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px; min-height: 14.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;">There are so many wonderful phenomena. The duality of light. The schrodinger's cat. Things that are to unbelievable to imagine. Case in point, the schrodinger's cat explanation led to this famous question of whether the moon exists if we don't look at it. Maybe it needs more imagination than what we understand because the senses we are provided with are not enough to imagine at such a level or maybe our own observations are changing the way it works. We don't know. Do we need to understand everything to get an answer to our question? How do we dig deeper into our understanding to know the answer which is just lying there waiting to be found out? How amazing is everything?</span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="font: 12.0px Times; margin: 0.0px 0.0px 0.0px 0.0px; min-height: 14.0px;">
<span class="Apple-style-span" style="font-family: Verdana, sans-serif;">Thus we continue in our journey for knowledge. I hope that one day we will be able to understand this universe and hence be able to provide a coherent answer to the question. Until then we walk</span></div>
</div>Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com1tag:blogger.com,1999:blog-1832447583505426662.post-81909163658610280362012-05-04T02:33:00.000-07:002012-05-04T02:33:07.101-07:00What is important and what is not.<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="separator" style="clear: both; text-align: center;">
<a href="http://4.bp.blogspot.com/-ER3XUH3Tj7M/T6OiQHdFLUI/AAAAAAAAAF4/Qo-aWxhkc_0/s1600/tree+of+knowledge.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="http://4.bp.blogspot.com/-ER3XUH3Tj7M/T6OiQHdFLUI/AAAAAAAAAF4/Qo-aWxhkc_0/s1600/tree+of+knowledge.jpg" /></a></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
It is in stark contrast, how the rich differ from the poor. The extravagance is so appalling. I have seen poor schools back home. I have seen their resources and how people study there. It was only recently that I saw a "rich" school. It raised a number of questions in me. What is the need for an XBOX 360 and LCD Tvs in a school? Why do people put money in buying xbox 360s in schools when many schools do not have benches for people to sit on? Who needs to learn the art of bowling and para sailing when other people do not have a foot ball to play with? How is the rich privileged to do what ever they want and the poor need to have do with whatever little they have? Why is it that it is the rich who complain and poor are content with what they have despite the responsibilities they shoulder, burdened upon them by the rich? How can the rich take ownership of the "resources" that is bestowed upon all of us by mother nature? How can mother nature be partial?<br /><br />Can mother nature be partial to her children? A mother loves all her children equally. So the greatest wealth she provides her children must be equal to all. This means that all these "resources" owned by the rich are not important to her. The gold and diamonds are just stones in her eyes. It doesn't matter to her when a few of her children get to play with shiny stones while others don't because they are just stones. She knows the air we breath is important and she gives it to everyone equally. She knows water is important and which she does provide for all her children. There is an Oasis even in a desert. <br /><br />There lies the fundamental answer to all the questions. What is important and what is not. The greatest wealth provided by nature are free for everyone to take. They are available for everyone equally. This wealth is common for all and cannot be taken away from man. It can only be given in abundance. The greatest resource is knowledge. It is knowledge that we must be after. Not extravagant richness and hanging chandeliers. Not huge houses or expensive cars but simple elegant knowledge. Obtaining knowledge is the means and it is the end, moving us from ignorance into light. <br /><br /></div>
</div>Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-75888579613879413612012-03-15T00:23:00.001-07:002012-03-15T00:23:58.274-07:00Hope<div dir="ltr" style="text-align: left;" trbidi="on">
<iframe width="560" height="315" src="http://www.youtube.com/embed/Y4MnpzG5Sqc" frameborder="0" allowfullscreen></iframe>
<br />
This is more than stopping Kony. This is a test for humanity.
</div>Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-4936434818889974582012-02-24T03:25:00.001-08:002012-02-24T03:25:26.219-08:00Biological Sequence Alignment using Parallel Prefix Algorithm implemented using FPGA<div dir="ltr" style="text-align: left;" trbidi="on">
Project Documentation<br />
<ul style="text-align: left;">
<li><a href="http://abishekramdas.blogspot.com/2012/02/fpga-implementation-of-biological.html">Introduction</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/fpga-implementation-of-biological.html">Important Terms</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/biological-sequence-alignment-needleman.html">Needleman-Wunsch Algorithm</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/parallel-prefix-algorithm-biological.html">Parallel Prefix Algorithm</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/parallel-prefix-methodology-biological.html">Parallel Prefix Methodology</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/vhdl-implementation-biological-sequence.html">VHDL Implementation</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/data-path-biological-sequence-alignment.html">Data Path</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/salient-features-biological-sequence.html">Salient Features</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/model-calculations-and-proof-of-concept.html">Model Calculations</a></li>
<li><a href="http://abishekramdas.blogspot.com/2012/02/vhdl-files-download-here-biological.html">Download source code</a></li>
</ul>
Hope this helps you as much as you have helped me.<br />
<br />
Abishek</div>Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-68193851304554994942012-02-24T02:38:00.000-08:002012-02-24T02:38:20.164-08:00Model Calculations and Proof of Concept Simulations - Biological Sequence Alignment<div dir="ltr" style="text-align: left;" trbidi="on">
MODEL CALCULATIONS<br />
<br />
The example under consideration is<br />
<div class="separator" style="clear: both; text-align: center;">
<a href="http://2.bp.blogspot.com/-mStjBviAPP0/T0dlFEsYzjI/AAAAAAAAAE4/EGPptlEBamg/s1600/table2_par_ref.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="141" src="http://2.bp.blogspot.com/-mStjBviAPP0/T0dlFEsYzjI/AAAAAAAAAE4/EGPptlEBamg/s400/table2_par_ref.png" width="400" /> </a></div>
<div class="separator" style="clear: both; text-align: center;">
<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="http://3.bp.blogspot.com/-AmpS-VxpsUw/T0dlkx3B9GI/AAAAAAAAAFA/rKLi35c9zwo/s1600/table3_par_ref.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="102" src="http://3.bp.blogspot.com/-AmpS-VxpsUw/T0dlkx3B9GI/AAAAAAAAAFA/rKLi35c9zwo/s400/table3_par_ref.png" width="400" /></a></div>
<div class="separator" style="clear: both; text-align: center;">
<br /></div>
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The Row 0 and Column 0 are assumed to be known.</div>
<div class="separator" style="clear: both; text-align: justify;">
<br /><b>Calculating Row 1</b><br />w[j] = max ((T[i-1,j] + f(ai , '-'), (T[i-1,j-1] + f(ai , bj))<br />w[1] = max((T[0,1] – 1), (T(0,0) + f(a1, b1)) = 0<br />w[2] = max((T[0,2] – 1), (T(0,1) + f(a1, b2)) = -1<br />w[3] = max((T[0,3] – 1), (T(0,2) + f(a1, b3)) = -2<br />w[4] = max((T[0,4] – 1), (T(0,3) + f(a1, b4)) = -3<br />w[5] = max((T[0,5] – 1), (T(0,4) + f(a1, b5)) = -6<br />w[6] = max((T[0,6] – 1), (T(0,5) + f(a1, b6)) = -5<br />w[7] = max((T[0,7] – 1), (T(0,6) + f(a1 , b7)) = -6<br />w[8] = max((T[0,8] – 1), (T(0,7) + f(a1, b8)) = -7</div>
<div class="separator" style="clear: both; text-align: justify;">
<br />z[j] = w[j] + y[j]<br />z[1] = w[1] -y[1] = w[1] +1 = 0<br />z[2] = w[2] -y[2] = w[2] +2 = 0 </div>
<div class="separator" style="clear: both; text-align: justify;">
z[3] = w[3] -y[3] = w[3] +3 = 0<br />z[4] = w[4] -y[4] = w[4] +4 = 0<br />z[5] = w[5] -y[5] = w[5] +5 = 0<br />z[6] = w[6] -y[6] = w[6] +6 = 0<br />z[7] = w[7] -y[7] = w[7] +7 = 0<br />z[8] = w[8] -y[8] = w[8] +8 = 0</div>
<div class="separator" style="clear: both; text-align: justify;">
<br /></div>
<div class="separator" style="clear: both; text-align: justify;">
(Compare with x_reg in the output)</div>
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<br />T[1,1] = x[1] + g[1] = x[1] - 1 = -1<br />T[1,2] = x[2] + g[2] = x[2] - 2 = -2<br />T[1,3] = x[3] + g[3] = x[3] - 3 = -3<br />T[1,4] = x[4] + g[4] = x[4] - 4 = -4<br />T[1,5] = x[5] + g[5] = x[5] - 5 = -5<br />T[1,6] = x[6] + g[6] = x[6] - 6 = -6<br />T[1,7] = x[7] + g[7] = x[7] - 7 = -7<br />T[1,8] = x[8] + g[8] = x[8] - 8 = -8</div>
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<br />Compare with outputs y0 to y7 in the simulated output. Row 1 values are calculated.</div>
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<b>Simulation of Row 1</b></div>
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<a href="http://2.bp.blogspot.com/-xGVRdJR9sVc/T0dmWeIekDI/AAAAAAAAAFI/SBN1PPLTg_k/s1600/simulation_row1_par_pref.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" height="640" src="http://2.bp.blogspot.com/-xGVRdJR9sVc/T0dmWeIekDI/AAAAAAAAAFI/SBN1PPLTg_k/s640/simulation_row1_par_pref.png" width="400" /></a></div>
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<b> </b>Row 1 values can be checked to be correct.(click to enlarge)</div>
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<b>Calculation of Row 2</b><br />
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Row 2<br />w[j] = max ((T[i-1,j] + f(ai , '-'), (T[i-1,j-1] + f(ai , bj))<br />
<br />w[1] = max((T[1,1] – 1), (T(1,0) + f(a2, b1)) = max(-2,-2) = -2<br />w[2] = max((T[1,2] – 1), (T(1,1) + f(a2, b2)) = -2<br />w[3] = max((T[1,3] – 1), (T(1,2) + f(a2, b3)) = -1 (note: f(a2, b3) = 1, match)<br />w[4] = max((T[1,4] – 1), (T(1,3) + f(a2, b4)) = -4<br />w[5] = max((T[1,5] – 1), (T(1,4) + f(a2, b5)) = -5<br />w[6] = max((T[1,6] – 1), (T(1,5) + f(a2, b6)) = -6<br />w[7] = max((T[1,7] – 1), (T(1,6) + f(a2, b7)) = -7<br />w[8] = max((T[1,8] – 1), (T(1,7) + f(a2, b8)) = -8<br />
<br />z[j] = w[j] - y[j]<br />z[1] = w[1] -y[1] = w[1] + 1 = -1<br />z[2] = w[2] -y[2] = w[2] + 2 = 0<br />z[3] = w[3] -y[3] = w[3] + 3 = 2<br />z[4] = w[4] -y[4] = w[4] + 4 = -4<br />z[5] = w[5] -y[5] = w[5] + 5 = -5<b> </b><br />
z[6] = w[6] -y[6] = w[6] + 6 = -6<br />z[7] = w[7] -y[7] = w[7] + 7 = -7<br />z[8] = w[8] -y[8] = w[8] + 8 = -8<br />(Compare with w_x_reg in simulated output)<br />
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After parallel prefix<br />
<br />x[1] = max( z[1]) = -1<br />x[2] = max( z[1], z[2]) = 0<br />x[3] = max( z[1], z[2], z[3]) = 2<br />x[4] = max( z[1], z[2], z[3], z[4]) = 2<br />x[5] = max( z[1], z[2], z[3], z[4], z[5]) = 2<br />x[6] = max( z[1], z[2], z[3], z[4], z[5], z[6]) = 2<br />x[7] = max( z[1], z[2], z[3], z[4], z[5], z[6], z[7]) = 2<br />x[8] = max( z[1], z[2], z[3], z[4], z[5], z[6], z[7], z[8]) = 2<br />(Compare with x_reg in the output)<br />
<br />T[1,1] = x[1] – g[1] = x[1] - 1 = -2<br />T[1,2] = x[2] – g[2] = x[2] - 2 = -2<br />T[1,3] = x[3] – g[3] = x[3] - 3 = -1<br />T[1,4] = x[4] – g[4] = x[4] - 4 = -2<br />T[1,5] = x[5] – g[5] = x[5] - 5 = -3<br />T[1,6] = x[6] – g[6] = x[6] - 6 = -4<br />T[1,7] = x[7] – g[7] = x[7] - 7 = -5<br />T[1,8] = x[8] – g[8] = x[8] - 8 = -6<br />Compare with outputs y0 to y7 in the simulated output. Row 2 values are calculated.<br />
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<a href="http://1.bp.blogspot.com/-YZyAVt_VNiA/T0dnZfYPsJI/AAAAAAAAAFQ/VJWoeHh9J_k/s1600/simulation_row2_par_pref.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" height="640" src="http://1.bp.blogspot.com/-YZyAVt_VNiA/T0dnZfYPsJI/AAAAAAAAAFQ/VJWoeHh9J_k/s640/simulation_row2_par_pref.png" width="400" /></a></div>
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The other values are calculated and documented in this table.<br />
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<a href="http://4.bp.blogspot.com/-uCocbM9oqqI/T0dn9AuYUuI/AAAAAAAAAFY/7YB82Ec9vy0/s1600/final_res_par_pref.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" height="157" src="http://4.bp.blogspot.com/-uCocbM9oqqI/T0dn9AuYUuI/AAAAAAAAAFY/7YB82Ec9vy0/s400/final_res_par_pref.png" width="400" /></a><a href="http://4.bp.blogspot.com/-uCocbM9oqqI/T0dn9AuYUuI/AAAAAAAAAFY/7YB82Ec9vy0/s1600/final_res_par_pref.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"> </a></div>
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They are in conformance with the values obtained in simulations.<br />
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<br /></div>Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0tag:blogger.com,1999:blog-1832447583505426662.post-79940115495281206442012-02-24T02:20:00.001-08:002012-02-24T02:20:25.707-08:00Salient Features - Biological Sequence alignment<div dir="ltr" style="text-align: left;" trbidi="on">
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SALIENT FEATURES OF THE PROGRAM<br />Finite state machine cycles through 4 states s0, s1, s2, s3. The states are indicated by a 2 bit counter (counter_2bit) which increments every clock pulse.<br />s0 = 00<br />s1 = 01<br />s2 = 10<br />s3 = 11<br />One cycle is one pass through the four states of the finite state machine.<br />For a particular row i, consider the scoring matrix RAM (w_ram). Assume the scores for the particular row are already available. Address to the RAM is generated by a 3 bit counter. Every s0, the address to the RAM is incremented. At s1 the read enable of the ram is made high. At s2, the scores for the next row are available in the outputs of the ram. Thus during the calculation of table entries for a particular row, the scores required for the next row are fetched from the memory and are available.</div>
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<br />While calculating the table entries of a particular row, the table entries of the previous row are already available in the s3 stage of the previous cycle. The parallel prefix module gets the z inputs during the falling edge of the s0 state. This is done so as to provide enough time for the combinational calculation of z[j]s from previous row table entries and values from scoring matrices. The z[j]s is available in w_x_reg at the rising edge of state 0. This value is latched on to x_ram during the falling edge of the same state. This is done so that the inputs to the parallel prefix module are available when it starts running at state s1.</div>
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<br />The parallel prefix algorithm then runs on the z[j] values stored in x_ram. The initial z[j] values are<br />available in its inputs during state s0. The parallel prefix algorithm starts executing at s1, goes to the second stage at state s2 and completes the operation in state s3. The appropriate control signals for the nodes are given based on the table described previously. 8 nodes are instantiated and their mode of operation is controlled by 8 bit control register dup_en. Each bit of this register control the appropriate node. At s1, node 0 is alone in the duplication mode and rest is in operation mode. In s2, node0, node1 are in duplication mode and rest in operation mode. In s3, node0, node1, node2, node3 are in duplication mode and rest is in operation mode. The appropriate dup_en signals are generated using shift_control logic. Thus at s3 the x[j] values are available.</div>
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<br />These x[j]s are connected to 8 signed 8 bit adders and added with 8 bytes of y[j] during the same state s1. This is done with minimum delay since it is a combinational circuit. The add_en signal is generated every s3 and it adds the 8 bytes of x[j]s to 8 bytes of y[j]s to get 8 bytes of table entries. These table entries are stored in table_ram as well as fed back to the w_calculation module to calculate w values for the next row.</div>
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<br />At state 1, table_ram is write-enabled and the 8 bytes of table entries are stored in the memory. By the end of state s3, previous row table entries and scoring matrix values for the next row are available at the inputs of w_calculation module. w_calculation module is enabled in state s0 of the next cycle. The combinational logic calculates values of z and they are latched on the inputs of parallel prefix module by the falling edge of the s0 state of the next cycle.</div>
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<br />This process is repeated 8 cycles to fill all entries of the table. the table generated at the end is optimized only to contain the calculated table values. Row0 and column0 values are not present in the table as they can be easily calculated.</div>
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<br /><b>TIME EFFICIENCY</b><br />Dynamic programming algorithms require O(mn) time to complete sequence matching. In this case matching 8 word query with a 8 word database, time taken by dynamic programming techniques would have been 64 clock pulses. But parallel prefix algorithm is much faster. Each cycle of the parallel prefix requires 4 clock pulses. Number of cycles in this particular case is 8. so the complete operation of sequence matching is done in a span of 32 clock pulses which is almost half the time required by dynamic programming algorithms. This is achieved by proper pipelining of the different stages. Pipelining is done so as to prefetch the values from memory, calculations are done in parallel for 8 bytes and writng in to the table is pipelined with calculation of w values for the next row. The control signals for both the RAMs, w_calculation module, the 8 nodes and the 8 signed adders are appropriately generated using the 2 bit counter as the reference.</div>
</div>Abishek Ramdashttp://www.blogger.com/profile/15162915377358767604noreply@blogger.com0