Poly SPARC

Hello, Scan insertion is the process of converting the flip flops present in a circuit into scan flip flops The flip-flops in the circuit, shown in Figure, are connected together in a chain to form a shift register, also called scan chain. This makes all flip-flops in the circuit controllable and observable leaving behind only the combinational logic to be tested.  During scan mode, the test vectors are shifted into (scan-in) the scan chain by shift operations. The test vectors are then applied to the combinational logic and the response is clocked back into the flip-flops. The response is then shifted out (scan-out) from the scan chain to test as the next test vector is being scanned in. This DFT converts the difficult to test sequential circuit into a fully combinational circuit. For large designs, the long chain is split into several smaller chains in order to cope with the large number of test patterns. The chains can have different lengths and the depth is define...

Hello, I am posting an old program here that was written by me to trace different paths in a circuit. It is written in Perl and works for verilog (.v) files. The program recursively iterates through every path in the circuit and it prints out the gates encountered en-route.  It is useful if you are calculating a metric for each gate/wire This is a way to NOT write a program. The program, as I found out later, is very slow because It does not build the data structure for gates that makes traversing easier It works with gate names instead of numeric abstractions which are easier to deal with.  The better way to traverse through a circuit is to build a data structure for each gate encountered. Each gate should be assigned a number and there must be arrays in the data structure that holds information on the gates at its input and output. This makes traversing in both directions easier. Sample data structure struct gate{ char name[]; int num_in; int num_out; int i...

Hello , When working with benchmark circuits, it is convenient to levelize the gates and work with levels. This is useful when you want to calculate some metric for all gates or wires. It is efficient than recursively traversing through all wires, gates, and fanouts.  Here I upload a program that levelizes the iscas bench marks.  It is written in perl. Use it the way you see fit and edit it if you find mistakes. Levelization 1. Assign level number 0 to all primary inputs 2. For each PI fanout Label that circuit line with level number of the PI   Queue the logic gate driven by that fanout line (I need a queue) 3. While queue is not empty dequeue the next logic gate in the queue   If all of the gate fanins are labeled with level numbers, then label the logic gate and its fanouts with maximum of input levels + 1. Queue all fanouts of the logic gate. Otherwise requeue the logic gate.  Algorithm - Levelization loop inputlist ...

Here is an equivalent fault collapsing program, The aim is to  read a combinational Verilog netlist file and perform equivalent fault collapsing for the circuit. The program does equivalent fault collapsing for the following gate types Two-input, one-output gates or One-input, one-output gates as follows: AND2X1 OR2X1 NAND2X1 NOR2X1 XOR2X1 INVX1 BUFX1 Upgrade: Fanouts need to be considered separately. upgrade the program to include fanouts also #!/usr/bin/perl #fault_collapsing.plx use warnings; use strict; my $bench_file = $ARGV[0]; my $file_name; my $circuit_name; my $element; my @input_array; my @output_array; my @wire_array; my @gates; my @sorted_gates; my @wire_struct; #my @fanout_test; my $num_inputs=0; my $num_outputs=0; my $num_wires=0; my $num_gates=0; #Test netlist file if($bench_file =~ /(.*).v/) { $file_name = $1; } else { print "Format of bench file name: circuit_name.v \n example : s1...

Program - Transition fault testing using pattern shifting Serial version of the program is described here in detail This is the program i had written for testing delay transition faults. I am trying to parallelize this program. DELAY TESTING OBJECTIVE slow to raise and slow to fall patterns are to be tested. to test a slow to rise fault- apply a sa1 pattern (for a modified netlist) followed by a sa0 pattern (for unmodified netlist) to test a slow to fall fault - apply a sa0 pattern (for a modified netlist) followed by a sa1 pattern (for unmodified netlist)                      pattern 1   pattern 2  Slow to rise    sa1         sa0        Slow to fall    sa0         sa1    pattern 1 - patterns for modified netlist pattern 2 - patterns for unmodified netlist Testing for faults A. fault pattern ge...

Hi, I am working towards parallelization of one of my own sequential program. The sequential program is used to generate test patterns for Delay testing. (Testing of the rise and fall delays in a circuit). It takes up a lot of time to run and is a massively parallel program. So parallelization is a good idea to achieve speed up. I gathered a few points on parallelization of the program from the book "Parallel programming for Multicore and cluster systems" by Thomas Rauber Gudula Runger, I present them here. Aim: To parallelize the transition fault testing program so that it runs on more than one processor Steps involved in parallelization 1. Decomposition of the computations : GOAL : of task decomposition is keeping all the processors busy at all times. a. Computations of the sequential algorithm are decomposed into tasks and dependencies between the tasks are determined.Tasks are the smallest units of parallelism. b. Task may involve accesses to shared address s...

Report on few techniques of Built In Self Test It was required of me to read and write a report on Built In Self Test. Reading and understanding the mathematical implications were very exciting. You can find the report in the following link https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0B4rJ5uMNHA9pNTkyODk2MjItN2QzZS00ZGIyLWE5NDgtZjZhMjIzMDZkNDBm&hl=en&authkey=CKHm7dQE Abishek Ramdas NYU Poly

Atalanta is an ATPG tool that is used to generate test patterns for combinational circuits. atalanta is a windows executable file. I am using Atalanta ATPG tool to generate the test patterns required for generating the Transition fault Test patterns RUNNING ATALANTA (LINUX) You need to have WINE installed to run windows executable binary. Created a symbolic link in the usr/bin to the atalanta.exe, name of the link s atalanta. (not necessary if you do not have root privilages) chmod u+x /place/atalanta/atalanta.exe cd /usr/bin sudo ln -s /place/atalanta/atalanta.exe ./atalanta COMMAND TO RUN ATALANTA atalanta [option] filename //put this in a shell script