Poly SPARC

Bharathiyar, for tamil people, needs no introduction. He was a great tamil poet and a contemporary of Rabindranath Tagore. The world had the good fortune of reading Tagore's beautiful lines as many were written in English but was not so lucky when it came to the poems of Bharathi.  Maybe Bharathi deserves better than what we can offer. Here is one of his songs, translated with not so much justice done. He lost his mother at a very early age. When the only picture he had that reminded him of her gets lost, to the love of his life, poetry, he says I have forgotten the lovely face, To whom can I show my grief my dear friend? Even if my heart remembers the vivd love, why has my memory failed to keep the face intact, my dear friend? The bee that thinks no more of nectar, The flower that consigns the sun to oblivion, The vegetation that fails to recollect the rain, Has never existed. Why am I the aberration my dear friend? What purpose do these eyes serve if I cannot remember the ...

Hello , When working with benchmark circuits, it is convenient to levelize the gates and work with levels. This is useful when you want to calculate some metric for all gates or wires. It is efficient than recursively traversing through all wires, gates, and fanouts.  Here I upload a program that levelizes the iscas bench marks.  It is written in perl. Use it the way you see fit and edit it if you find mistakes. Levelization 1. Assign level number 0 to all primary inputs 2. For each PI fanout Label that circuit line with level number of the PI   Queue the logic gate driven by that fanout line (I need a queue) 3. While queue is not empty dequeue the next logic gate in the queue   If all of the gate fanins are labeled with level numbers, then label the logic gate and its fanouts with maximum of input levels + 1. Queue all fanouts of the logic gate. Otherwise requeue the logic gate.  Algorithm - Levelization loop inputlist ...

"I will go to paradise" he thought. Sitting there with the gun in his pocket in the jeep. He was waiting. "When do they come?" his friend asked. "4:30" he said keeping his mind focused on the task he had been given. "I will go to paradise and I will be under the feet of the almighty. I will be freed from my sins since I am doing this for him." he thought. "but....". He had long stopped listening to the tiny squeeky voice inside his head. Whenever he was on a mission dictated to him by god, the voice was there. A voice at a pitch slightly higher than his voice. The voice always questioned him. It always started with a but. He had learnt to control it. He was taught to not listen to the voice. "It is the devil" they told him when he was all but 14. "If you listen to the voice, you will be condemned for all eternity to hell. you will be burning in brimstone. You will know only pain and suffering". His tiny mind was a...

OpenSPARCT1 comes with a built in script called rsyn that is used to synthesize the required verilog files using synopsys design compiler. All the modules are individually compiled (except the mega cells) and you get the flattened and hierarchical verilog netlist file for individual modules.  You do not have the netlist file for the entire OpenSPARCT1 yet and that has to be done manually.   Important Scripts provided by SUN The OpenSPARCT1/design/sys/synopsys/script folder contains the scripts to configure and run synopsys   There are two configuration files     1. io configuration - project_io_cfg.scr     2. sparc configuration - project_sparc_cfg.scr  they contain the configuration information. Rsyn flow The rsyn command calls identifies the tool that is to be used and then calls the "rsyn,1.0" file in OpenSPARCT1/tools/perlmod 1. The rsyn file reads the block list that is present in OpenSPARCT1/design/sys/synopsys/. 2. It run...

It would be required to synthesize individual blocks in SPARC separately. For example, the method to synthesize the Load Store Unit is described here. You need to have successfully run rsyn - how? example lsu unit present in design/sys/iop/sparc/lsu Steps 1. Create a work folder anywhere you like 2. cd into design/sys/iop/sparc/lsu 3. Use the following script to collect the flat_files from the location 4. Use the following script to extract the flat nestlist from all modules inside lsu to a folder called flat_files Script: file_collect.sh (location /design/sys/iop/sparc/lsu) cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu/flat_files done 5. copy the files that are present in ...

List of files to compile sparc core in design vision present in design/sys/iop/sparc/flat_files bw_clk_cl_sparc_cmp_flat.v lsu_stb_rwctl_flat.v sparc_ffu_ctl_flat.v sparc_ifu_invctl_flat.v spu_lsurpt_flat.v cpx_spc_buf_flat.v lsu_stb_rwdp_flat.v sparc_ffu_dp_flat.v sparc_ifu_mbist_flat.v spu_madp_flat.v cpx_spc_rpt_flat.v lsu_tagdp_flat.v sparc_ffu.v sparc_ifu_sscan_flat.v spu.v lsu_dcdp_flat.v lsu_tlbdp_flat.v sparc_ffu_vis_flat.v sparc_ifu_swl_flat.v tlu_hyperv_flat.v lsu_dctldp_flat.v lsu.v sparc_ifu_dcl_flat.v sparc_ifu.v tlu_incr64_flat.v lsu_dctl_flat.v sparc_exu_alu_flat.v sparc_ifu_dec_flat.v sparc_ifu_wseldp_flat.v tlu_misctl_flat.v lsu_excpctl_flat.v sparc_exu_byp_flat.v sparc_ifu_errctl_flat.v sparc_mul...

--> You need to have successfully run rsyn - how? Sparc has a number of blocks. bw_clk_cl_sparc_cmp cpx_spc_buf cpx_spc_rpt exu ffu ifu lsu mul spu tlu spc_pcx_buf    Steps are 1. collect all the flattened netlist files from each block in work folder file_collect.sh - location design/sys/iop/sparc cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/ for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files done cd design/sys/iop/sparc mkdir flat_files ./file_collect.sh All the flat files in the sparc folder are present in /design/sys/iop/sparc/flat_files 2. collect the top level files from each of the blocks you will find the top level blocks for each module in the rtl folder inside that module current fldr - design/sys...