OpenSPARC Synthesis using Design Compiler

OpenSPARCT1 comes with a built in script called rsyn that is used to synthesize the required verilog files using synopsys design compiler. All the modules are individually compiled (except the mega cells) and you get the flattened and hierarchical verilog netlist file for individual modules.  You do not have the netlist file for the entire OpenSPARCT1 yet and that has to be done manually.

 
Important Scripts provided by SUN

The OpenSPARCT1/design/sys/synopsys/script folder contains the scripts to configure and run synopsys
 
There are two configuration files
    1. io configuration - project_io_cfg.scr
    2. sparc configuration - project_sparc_cfg.scr 
they contain the configuration information.

Rsyn flow
The rsyn command calls identifies the tool that is to be used and then calls the "rsyn,1.0" file in OpenSPARCT1/tools/perlmod

1. The rsyn file reads the block list that is present in OpenSPARCT1/design/sys/synopsys/.
2. It runs the synthesis for each block and stores the synthesized files in /design/sys/iop/$block/synopsys folder for each block
3. To do this it calls the run.scr file
This synthesizes all the files in the block list.


Here I describe different processes. If you feel the method is not right and changes are to be done. kindly let me know. 


Have fun,
Abishek

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