Synthesizing the entire OpenSPARCT1 processor using design-vision (design compiler)



If we are required to find area information or the routing information of the entire processor (with all 8 cores etc) we have to manually compile the flattened netlist file with the top level file of the processor. The procedure is described here.

The top level module for OpenSPARCT1 is “iop.v” located at design/sys/iop/rtl

Synthesize the whole processor using design vision
I need the area information of the processor with all 8 cores

1. Run rsyn to generate all the flattened netlist - how?
2. collect all the flattened netlist file in a folder

File: file_collect.sh
Location ~/opt/OpenSPARCT1/flat_files

cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop
for FILE in $(find . -type f | grep -e "flat")
do
echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files"
cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files
done

3. The top level file for the entire OpenSPARC chip is present in design/sys/iop/rtl and is called iop.v.
The processors and their connections are instantiated in this file.
This file does not instantiate the processors or other modules because of "ifdef" conditions (look inside iop.v)
We need to define our requirements (number of processors required, other hardware required) and I defined them in iop.h (design/sys/iop/include)

For example to instantiate all 8 SPARC cores, we need to add the following lines in iop.h
`define RTL_SPARC0 1
`define RTL_SPARC1 1
.
.
.
`define RTL_SPARC7 1

Other ifdef conditions are present in iop.v. In my case I defined everything to be 1.
alternatively you can remove the ifdef conditions in iop.v

4. This modified top level file (iop.v) file is added to the flat_files folder
5. design_vision is started inside a working directory,
6. The configuration synopsys_dc.setup script is run – sample dc_script file
7. Analyze all the files that are there in the flat_files folder (File -> Analyze)
8. Elaobrate the design with OpenSPARCT1 as the top module. (File -> Elaborate)
If there are unresolved references other than the memory modules (bw_r*), find those modules and add them to the flat_files folder.
Analyze the unresolved references and elaborate until references to memory modules only remain
9. Compile Design to generate the area information

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