Sunday, August 25, 2013

Job Hunt 101 - Cover Letter how to?

There will come different scenarios where you need to communicate with people. Writing a letter from scratch every time is time consuming. Having a template and modifying it to suit your purpose saves time and is easier. Here I have suggestions on what templates to prepare and samples.

You need to prepare templates for

    * Cover letter,
    * An email cover letter and
    * A linkedin inmail if you plan to use linkedin.


COVER LETTERThe cover letter can be in the doc or pdf format, doc is preferable as computerised searches are done in doc files. Having a cover letter helps you in the following ways

  1. When computer searches for relevant terms, chances are that it might find it in your cover letter if not on the resume. So do not replicate the resume data in the cover letter. Use the cover letter to compliment your resume.
  2. If it passes through the computer search and your resume is visible to recruiter/HR, they will read your cover letter to understand better your qualifications.
  3. It can help the hiring manager asses your strengths and if written well, is a showcase of your writing skills.

The cover letter can be a page long with 3-4 paragraphs. You need to begin with your interest in the company, the position you are applying for and how you came to know about this position. Here is a comprehensive tutorial on writing cover letters.

TUTORIAL ON WRITING COVER LETTERS - http://www.wikihow.com/Write-a-Cover-Letter

EMAIL COVER LETTER
You might have to send emails to recruiters, HR, hiring manager, people you know, people you find in monster.com etc when you are forwarding your resume. Say you come across a position that interests you in DICE.com, you find the email of the person posting the resume. It is advantageous to fill in the DICE application form and also send in your resume to the email address mentioned.

An email cover letter would help you introduce yourself and pique the hiring person's interest in you. It cannot be long winding stories it has to be precise and sharp. My cover letter had been evolving over the period of my application, the format I used is
  • A sentence describing the position I am applying for, the company; expressing my interest
  • A sentence on my work experience
  • 3-4 bullet points showing a few project experience. PLEASE NOTE I use the terms that are mentioned in the job description in these points so as to build interest in my profile. These are the terms the recruiter will be looking for.
  • My interest in talking to him
  • signature and dont forget the PHONE NUMBER

SAMPLE

I would like to express my interest in a position as anPOSITION at your company. My experience as POSITION 1 for 3 years and POSITION 2 for 2 years has provided me with the necessary skills required for the job. I am listing a few of them here

  • Implemented Test Access Mechanism (TAM) and TPM (security hardware) onto openSPARCT1 SoC, contains more than a million lines of verilog RTL, used modelSIM, Synopsys design compiler, place and route. Synopsys Prime Time
  • Developed a complete System on chip - obstacle avoidance SoC, integrated open8, memory and a custom developed processor. Used Cadence tools - RTL Compiler, Virtuoso. LVS and DRC done.
  • Developed Design for Test (DFT) hardware to detect small delay defects.
  • Published 3 papers in international conferences.

I would like to talk to you regarding the position. Thank you very much for your time.
Thanks,
Signature
Phone Number


LINKEDIN inmail
This must not be wordy and must be precise since the person you are sending it to is assumed to know what he is looking for. Use the same format as email cover letter but put in relevant points without too much technical terms. Follow the cause action result format.

Sample 
Dear hiring manager,

I came across a requirement for a POSITION at your company and I feel I am a good fit for this position.

  • 3 years experience as a EE Engieer with a masters in computer engineering from University (GPA 3.7/4).
  • Developed a Test access mechanism for System on Chips that reduced yield loss from >5% to 0.1%
  • Developed Design for Testability hardware that improved error coverage for small delay defects from 80% to 94%
  • Experienced in JTAG boundary scan 1149.1, BIST, MBIST, SoC Testing 1500, low power design techniques, asynchronous design techniques. Knowledge on Automatic Test Equipments (ATE).

I would like to be considered for this position. Kindly have a look at my profile.

Thank you for your time.
Name,
Phone number

Having these ready will make it easier to communicate with people.

Best of luck.

Sunday, August 11, 2013

Job Hunt 101 - Doc Prep - Resume How To?

The resume must be able to land you interview calls. Your resume must successfully be able to navigate through
  1. Recruiters, consultants
  2. Human Resource
  3. Hiring Manager
  4. Technical Team
I know you will ace the technical rounds if you are able to get through the hierarchy of recruiters, HR people etc. Your resume must help you climb this ladder. 

You can have an aesthetically pleasing resume/CV which does not have a lot of information on them but is very neat. This can help you with an academic position but in the industry, you are one amongst the million talented people who can get the job done. Here an aesthetically pleasing resume wont be able to help you. 

Your resume must have a lot of data. This data must be able to satisfy the requirements of the Recruiters, must poke the interest of the HR and must show your accomplishments to the technical people who are going to be interviewing you. 

Recruiters, Human Resource - 
Most recruiters are not going to be domain experts. The most probably dont understand what you have written in your resume. They might not even read it fully. They decide to continue/reject your application by doing a search for important terms required for the job. So being data intensive is good. Including the right keywords in your resume is the best way to navigate this course.
Case in point, I found a job that seemed perfect for my qualifications but it got rejected at this level because they were not able to find an obscure acronym they were looking. I had not added it because it seemed too general and thought by looking at my work, they will realize that I was THE guy they wanted. Sadly they did not understand what I had written which is understandable since they are not working in my domain. I included the keyword and got selected for next round. 

Hiring Manager, Technical People
Being data intensive is good but being repetitive is not. When actual technical people read your resume, they would like to see results, problems solved, improvements and not just obscure terms and tools. 

Here I am describing a format that will help you achieve these results. 
  1. Format
    1. Name, contact phone number, address - Important so that people will be able to contact you
    2. Objective statement 
    3. work experience, chronological order starting with latest experince
    4. Education, chronological order starting with highest degree
    5. Software/Tools/Hardware skills
    6. Publications
    7. Certifications
    8. Achievements
    9. Reference
    10. Blog list - work sample
Name, Contact phone number, address - Mail Address, Phone number so that people will be able to contact you

Objective Statement - A concise statement that clearly states what industry you are targeting and what your objective is. Sample objective statement - "To secure a position with a leading semiconductor organization, that will enable me to use my strong
engineering skills and education background and ability to work well with people". 
Sample objective statements can be found here - http://jobsearch.about.com/od/sampleresumes/a/sampleobjective.htm

Work Experience 
Recruiters are going to look if you have experience in the job you are applying. So list your experience in chronological order with the latest experience on top. A title and description are in order for each position you held.
  • Title:  
    • You have to mention your designation, 
    • company you work for and 
    • your start and end dates, to quantify your experience. 
    • Ex - DFT Engineer, New York University ,08/2010 - 06/2013
  • Description: After you mention these details, you need to describe the work you have been doing in that company. You will have worked on a number of projects, you should include a description for each of these projects. You can follow the CART rule when describing your work. 
    • Cause - The problem you worked on
    • Action - What you did to address the problem
    • Result -  Quantifiable improvements you achieved. USE NUMBERS TO SHOW RESULTS.
    • Tools used  
    • Example - Design for Testability hardware to improve Small Delay Defect coverage: Designed DfT hardware, developed placement algorithm that improves small delay defect coverage from 80% to 94%. Static and statistical timing analysis, timing closure was done, C and Perl was used. 
  • Notes
    • Make sure you mention tools used in the description, Recruiters recruit for a large number of positions and you cannot expect them to be knowledgeable in your domain. Most often the do not know understand your significant accomplishments. They search for tools and key words in your resume. Make sure you identify important key words pertaining to your domain and include them in your description. For example in the above statement I have used DfT, Static Timing Analysis, Timing closure, C and Perl which are highly searched keywords in my domain. 
    • It is not possible to include all the tools, 3 letter acronyms you have worked with into your resume. I suggest you have one line in the end of your description where you can add tools, acronyms that you are familiar with and mentioned in the job description. You modify this line to include important key terms mentioned in the job description. Presence of these key terms satisfies the recruiters enough to forward your resume to the next stage in the pipeline. Ex - Knowledge in interfaces PCI, PCIe, Ethernet and USB, Have used logic analyzer, oscilloscopes, multimeter. Note keywords PCI PCIe have been added because it is required in the job description and I have worked with them.
Education
List your education in chronological order starting with highest degree on top. If you have a PhD, Masters or Bachelors, you do not have to include school information. Mention the 
  • Degree,
  • Major 
  • University, 
  • Graduation year, 
  • GPA - mention only if high. If you feel it is low, dont mention it. 
  • Ex - Master of Science, Computer Engineering, NYU Poly, 2013, 3.76
Software/ Hardware Skills
Make sure you mention the tools you have used and familiar with. Make this list as comprehensive as possible because recruiters are going to be searching for specific tools which you might have used. If you have it there, chances are that he will forward your resume

Publications
  • List your publications in chronological order. 
  • Include the ones you have submitted and waiting for results, mention that it has been submitted. 
  • Do not include work in progress.
  • Format
    • Authors - some one might know your co-authors,
    • Name of the paper,
    • Conference to which it is submitted to
    • Year of publication 
  • Ex - Abishek Ramdas, Samah Saeed, Ozgur Sinanoglu. Design-for-Testability for Small Delay Defects. International Testing Conference, 2013, Submitted.
  • If you have submitted a Thesis, include the thesis in a separate section.
Certifications
  • List in chronological order
  • Certificate name
  • Entity issuing the certificate
  • Certificate number if applicable 
  • Ex - Nanoelectronics, Atomic Force Microscopy, Nanoscale Transistors, Purdue University, USA.
Achievements
  • Include affiliations, memberships - Ex Affiliated to IEEE
  • In achievements involving competition, express your rank as compared to total number of competitors in a competition
  • Ex - Ranked 376 from over 1,50,000 engineers in All India Graduate Aptitude Test for Electrical Engineers.
Blog
  • Include the web address of your blog, make sure you create an hyperlink 

Important Check List
  • Do not make your resume sound repetitive, do not include same information in different sections. 
  • No spelling and grammar mistakes. Do a spell check
  • Before sending out your resume make sure you look at the job description and add term, tools, 3 letter acronyms you feel important, to the extra line mentioned earlier.
  • The case is that you might be traveling around when searching for a job. Have a separate resume for different locations and send a resume that is closest to the job location.
  • You need your resume in doc and text format. Having it in PDF format makes it less searchable is what I hear. So uploading it in either doc format or text format is better for computerized searching of your resume.

Job Hunt 101 - Doc Prep - Pre-Doc Prep

Aim of this step is
  • Accessing your skills, experience and accomplishments. 
  • Getting data ready that you can use to fill online application forms easily
  • Help in resume preparation
  • Help in the HR, hiring manager round of interview

1. JOB SKILLS
LISTING - Start with the latest project and work your way down to the oldest project you can remember. 
Example - 
List of projects
  1. Testing chips using spare identical cores
  2. DFT for SDD
  3. Etc....
STATEMENTS - For each of these projects collect the following information in a table
  • Title:  
    • You have to mention your designation when doing the project, 
    • company you work for and 
    • your start and end dates, to quantify your experience. 
  • Statement: A brief desciprtion about the problem you worked on with numbers showing the effectiveness of your work
Example - consider
Testing chips using spare identical cores - Developed Test access mechanism to test multi core chips 
and 
Testing chips using spare identical cores - DFT Engineer, New York University ,08/2010 - 06/2013 - Developed a test access mechanism and design for testability scheme to test multi-core chips. I was able to reduce the yield loss from 6% to 0.1%, saving upto $1.5M annually. 

See how the second statement with numbers improve the strength of your statement.


2. PERSONAL SKILLS
LISTING - Identify 10 personal skills that you feel you possess http://www.illinoisworknet.com/vos_portal/Archives/Documents/Personal_Skills_Checklist.htm
Of these 10 choose 5 skills that applies most to you
STATEMENTS - Write statements that describe the situation where you have used the skill, Use numbers to show effectiveness of work.  

3. How I am different from others?
Have 3-4 statements why you think you are different from others. You can state your skills, accomplishments etc
Example - 
  • Extensive hands-on knowledge in VLSI system design, architecture and Testing.
  • Fluent with ASIC Design flow, worked with Cadence and Synopsys design tools.
  • Published 3 papers at well known conferences in the field of VLSI Testing.
  • Knowledgable in device physics, quantum mechanics, atomic transport, nanoscale device modeling. 
4. Keyword List
A list of keywords that can be used to search for positions on various job boards. 
Sit for some time and brainstorm important terms, acronyms, tools, designations, languages, concepts that you think
  • important in your domain
  • you have experience with
  • are needed in the industry
  • Is contained in search terms for common positions in the industry
Ex - My domain as DFT Engineer, These are common terms I use to search for positions 
Cadence, encounter, virtuoso, RTL compiler, Synopsys, Tetramax, Design compiler, RTL, vhdl, verilog, verification, synthesis, place and route, layout, clock tree, openSPARC, DFT, DFX, ATPG, BIST, Design for test, boundary scan, VLSI, Testing, FPGA, VIrtex, spartan, modelSIm, Xilinx, ISE, EDk, chipscope, SRAM,  PIC, microcontroller, MPLAB, assembly, mpasm, C, I2C, SPI, Ethernet, USB, Perl, Matlab, signal processing, JMP, SAS, logisim, gate level simulation, SoC

5. Transcripts, Certificates, Publications, Thesis, Project documents
In a folder, collect all your transcripts,certificates, Publications, Thesis and Project documents. For certain positions, You might need to submit a few of these documents. They can be used as a reference for later on.

6. List of Companies
Brainstorm a list of companies in your domain that you would like to be placed in a spreadsheet.

7. List of References
Create a spreadsheet with atleast 3 references with their 
  • names, 
  • designation, 
  • phone number
8. List of Contacts
Brainstorm a list of people you know and who can help you in forwarding your resume internally. Have an excel sheet with 3 columns, Company, Name, designation, contact information (email, phone) and add them to a spreadsheet.


Job Hunt 101 - Document Preparation

The first step of the preparation process is to get your documents ready and easily available when needed. There are a number of documents we need to have for a successful application. Here we discuss the documents and how they can be prepared. 

The steps involved are
  1. Pre-document preparation
  2. Resume
  3. Cover letter
  4. E-Mail cover letter 
  5. Linkedin in-mail letter
Click on the links to get started. 

Thanks,
Abishek

Job Hunt 101

Hello, 

I am a new college graduate and was looking for my first job. I had to walk, skip, fall and learn from my mistakes before I got my dream job. It took me a lot of preparation and a lot more patience for me to land it. I understand how difficult it is for you and so I am creating a series of guides that has tips and information on what I had learnt in the process of searching for a job. I list strategies that might be useful for you to turn your luck around. These tips are aimed at getting the maximum benefit of every opportunity that comes our way. Being prepared is the best way to land the job. 

Aim
  • To provide you with tips and tricks that I had learnt in the process of searching for a job. 
  • To learn from your feedback and experience.
I plan to address the following topics which have subtopics in them (click on them to view)
I wish you the best of luck in your journey. 
Thanks,
Abishek
PS - This is a work in progress

Saturday, June 22, 2013

Scan Insertion

Hello,

Scan insertion is the process of converting the flip flops present in a circuit into scan flip flops
The flip-flops in the circuit, shown in Figure, are connected together in a chain to form a shift register, also called scan chain. This makes all flip-flops in the circuit controllable and observable leaving behind only the combinational logic to be tested. 

During scan mode, the test vectors are shifted into (scan-in) the scan chain by shift operations. The test vectors are then applied to the combinational logic and the response is clocked back into the flip-flops. The response is then shifted out (scan-out) from the scan chain to test as the next test vector is being scanned in. This DFT converts the difficult to test sequential circuit into a fully combinational circuit.

For large designs, the long chain is split into several smaller chains in order to cope with the large number of test patterns. The chains can have different lengths and the depth is defined by the length of the longest chain. This splitting of the scan chain increases the test speed because several chains can now be operated in parallel but has the added cost of additional pins and channels. 

You can use commercial tools like Synopsys Tetramax to do scan insertion for you. Otherwise you can write your own script that does scan insertion. Here is a script that converts DFF to Scan DFF in a verilog file. The name of the scan flip-flop and necessary connections can be identified using the library. Flip flops are identified, their names changed, connections re-connected and additional pins are added at the primary input.

PERL SCRIPT THAT DOES SCAN INSERTION
  
 #!/usr/bin/perl  
 #scan_insertion.plx  
 use warnings;  
 use Data::Dumper;  
 use List::Util qw(min);  
 my $bench_file = $ARGV[0];  
 my $file_name;  
 #Test netlist file  
 if($bench_file =~ /(.*).v/){  
 $file_name = $1;  
 }   
 else{  
 print "Format of bench file name: circuit_name.v \n example : s1423.v\n";  
 }  
 $file_name_scan_ins = $file_name.'_scan_inserted.v';  
 open($FILEREAD, $bench_file) or die "could not open file to read";  
 open($FILEWRITE, '>', $file_name_scan_ins) or die "Could not open\n";  
 #Read Netlist File - count #FF  
 while(<$FILEREAD>){  
   my $INPUT_DATA = $_;  
   chomp($INPUT_DATA);  
   if($INPUT_DATA =~ m/^\s*(DFFX1)\s*(.*)\s*\(\.CK\((.*)\),\s*\.D\((.*)\),\s*\.Q\((.*)\)\);$/){  
      $count++;  
   }  
 }  
 close(FILEREAD);  
 #Modify netlist  
 $max_count = $count;  
 my $modified_data;  
 my $prev_op;  
 open($FILEREAD, $bench_file) or die "could not open file to read";  
 while(<$FILEREAD>){  
   $INPUT_DATA = $_;  
   chomp($INPUT_DATA);  
   if($INPUT_DATA =~ /module\s*(.*)\s*\((.*)\);/){  
      $circuit_name = $1;  
      print $FILEWRITE "module "."$1 "."($2,scan_data_in,scan_data_out,scan_enable);\n";  
   }  
   elsif($INPUT_DATA =~ /^\s*input\s*(.*);/){  
      print $FILEWRITE "input ".$1.",scan_data_in,scan_enable;"."\n";  
   }  
   elsif($INPUT_DATA =~ /^\s*output\s*(.*);/){  
      print $FILEWRITE "output ".$1.",scan_data_out;"."\n";  
   }  
   elsif($INPUT_DATA =~ m/^\s*(DFFX1)\s*(.*)\s*\(\.CK\((.*)\),\s*\.D\((.*)\),\s*\.Q\((.*)\)\);$/){  
      if($count == $max_count){  
        print $FILEWRITE "S_DFFX1"." ".$2."(.CK($3),.D($4),.SE(scan_enable),.SI(scan_data_in),.Q($5));\n";  
        $prev_op = $5;  
      }  
      else{  
        print $FILEWRITE "S_DFFX1"." ".$2."(.CK($3),.D($4),.SE(scan_enable),.SI($prev_op),.Q($5));\n";  
        $prev_op=$5;  
        if($count == 1){  
           print $FILEWRITE "BUFX1 scan_buff_op (.A($5),.Y(scan_data_out));\n"  
        }  
      }  
      $count--;  
   }  
   else{  
      print $FILEWRITE $INPUT_DATA."\n";  
   }  
 }  
 close(FILEREAD);  
 close(FILEWRITE);  
 



Path Trace

Hello,

I am posting an old program here that was written by me to trace different paths in a circuit. It is written in Perl and works for verilog (.v) files.

The program recursively iterates through every path in the circuit and it prints out the gates encountered en-route.  It is useful if you are calculating a metric for each gate/wire

This is a way to NOT write a program. The program, as I found out later, is very slow because
  • It does not build the data structure for gates that makes traversing easier
  • It works with gate names instead of numeric abstractions which are easier to deal with. 
The better way to traverse through a circuit is to build a data structure for each gate encountered. Each gate should be assigned a number and there must be arrays in the data structure that holds information on the gates at its input and output. This makes traversing in both directions easier.

Sample data structure
struct gate{
char name[];
int num_in;
int num_out;
int in[];
int out[];
.
.


You need to traverse the netlist once to fill in the data structures and you are good to go.

I cannot post the better program here because it was not written by me. So I post my old version of path trace here.
 #!/usr/bin/perl  
 #Path_Trace.plx  
 use warnings;  
 use Data::Dumper;  
 use strict;  
 use List::Util qw(min);  
 my $bench_file = $ARGV[0];  
 my $file_name;  
 my $circuit_name;  
 my $element;  
 my @input_array;  
 my @output_array;  
 my @wire_array;  
 my @gates;  
 my @sorted_gates;  
 my @wire_struct;  
 my @input_list_struct;  
 my @input_list_struct_2;  
 my @output_list_struct;  
 my @gate_queue;  
 #my @fanout_test;  
 my $num_inputs=0;  
 my $num_outputs=0;  
 my $num_wires=0;  
 my $num_gates=0;  
 my $gate_name_temp;  
 my $gate;  
 my $line;  
 my $role;  
 my $inp;  
 my $inp_test;  
 #Test netlist file  
 if($bench_file =~ /(.*).v/)  
 {  
 $file_name = $1;  
 }   
 else  
 {  
 print "Format of bench file name: circuit_name.v \n example : s1423.v\n";  
 }  
 #Read Netlist File  
 while(<>)  
 {  
   my $INPUT_DATA = $_;  
   chomp($INPUT_DATA);  
 {  
 #MODULE NAME  
 if($INPUT_DATA =~ /module (.*) (.*);/)  
 {  
   $circuit_name = $1;  
   print "circuit name = $circuit_name\n";  
 }  
 #INPUT OUTPUT WIRES  
 if($INPUT_DATA =~ m/^\s*input (.*);/)  
 {  
   @input_array = split /,/, $1;  
 }  
 if($INPUT_DATA =~ m/^\s*output (.*);/)  
 {  
   @output_array = split /,/, $1;  
 }  
 if($INPUT_DATA =~ m/^\s*wire (.*);/)  
 {  
   @wire_array = split /,/, $1;    
 }  
 my @wire1;  
 my @wire2;  
 my @wire3;  
 my $gate_name_temp;  
 my $gate;  
 my $line;  
 my $role;  
 #AND, OR, NAND, NOR, XOR  
 if($INPUT_DATA =~ m/^\s*(NAND2X1)\s*(.*)\s*\(\.Y\((.*)\),\.A\((.*)\),\.B\((.*)\)\);$/)  
 {  
   push @gates,   
   {   
      element => "gate",  
      num_inputs => 2,  
      gate_type => "$1",   
      gate_name => "$2",   
      output =>   
      {  
        element => "wire",  
        wire_name => "$3",  
        sa0 => 1,  
        sa1 => 1,  
        level => 0,  
        wire_delay =>0,  
      },  
      input_1 =>   
      {  
        element => "wire",  
        wire_name => "$2_$4",   
        sa0 => 1,  
        sa1 => 1,  
        level => 0,  
        wire_delay => 0,  
      },  
      input_2 =>   
      {  
        element => "wire",  
        wire_name => "$2_$5",   
        sa0 => 1,  
        sa1 => 1,  
        level => 0,  
        wire_delay => 0,  
      },  
      processed => 0,   
      gate_delay => 2,  
      gate_level => -1  
   };  
 }  
 #INV, BUF  
 #DE - Doesnt Exist  
 #renaming the gates at inputs of the gates for fanouts  
 if($INPUT_DATA =~ m/^\s*(INVX1|BUFX1) (.*) \(\.Y\((.*)\),\.A\((.*)\)\);$/)  
 {  
   $gate_name_temp = $2;  
   push @gates,   
   {   
      element => "gate",  
      num_inputs => 1,  
      gate_type => "$1",   
      gate_name => "$2",   
      output =>   
      {  
        element => "wire",  
        wire_name => "$3",  
        sa0 => 1,  
        sa1 => 1,  
        level => 0,  
        wire_delay => 0,  
      },  
      input_1 =>   
      {  
        element => "wire",  
        wire_name => "$2_$4",   
        sa0 => 1,  
        sa1 => 1,  
        level => 0,  
        wire_delay => 0,  
      },  
      processed => 0,   
      gate_delay => 1,  
      gate_level => -1  
   };  
 }  
 }  
 }  
 #File Read complete  
 #wire struct holds fault data for all wires  
 #input_list_struct is used for levelization  
 for $element (@input_array){  
   push @wire_struct, {element => "wire",wire_name => "$element", sa0 => 1, sa1 =>1, level => 0,wire_delay=>0};  
   push @input_list_struct, {element => "wire",wire_name => "$element", sa0 => 1, sa1 => 1, level => 0,wire_delay=>0};  
   push @input_list_struct_2, {element => "wire",wire_name => "$element", sa0 => 1, sa1 => 1, level => 0,wire_delay=>0};  
 }  
 for $element (@wire_array){  
   push @wire_struct, { element => "wire",wire_name => "$element", sa0 => 1, sa1 =>1, level => -1,wire_delay=>0};  
 }  
 for $element (@output_array){  
   push @wire_struct, { element => "wire",wire_name => "$element", sa0 => 1, sa1 =>1, level => -1,wire_delay=>0};  
   push @output_list_struct, {element => "wire",wire_name => "$element", sa0 => 1, sa1 => 1, level => 0,wire_delay=>0};  
 }  
 $num_gates = scalar @gates;  
 my $index=0;  
 #gate_processed = 2 then all inputs are processed  
 #shift gate into the queue if even one of the inputs processed  
 while($num_gates != 0)  
 {  
   for my $gate(@gates){    
      for my $inp (@input_list_struct){  
        my $inp_test = $inp->{wire_name};  
        if(($gate->{input_1})->{wire_name} =~ m/$inp_test$/){   
           $gate->{processed}++;  
           if($gate->{processed}==1){  
             unshift(@gate_queue,$gate);  
           }  
           if($gate->{processed}>1){  
             $gate->{processed}=$gate->{num_inputs};  
           }  
        }  
        if(($gate->{num_inputs}!=1)){  
           if(($gate->{input_2})->{wire_name} =~ m/$inp_test$/){  
             $gate->{processed}++;  
             if($gate->{processed}==1){  
                unshift(@gate_queue,$gate);  
             }  
           }  
           if($gate->{processed}>1){  
             $gate->{processed}=$gate->{num_inputs};  
           }  
        }  
      }  
   }    
 #if both inputs of the gates are processed, then calculate the level of the gate  
 #if only one of the inputs are processed, then add the gate to the end  
   my $num_gate_queue = scalar @gate_queue;  
   while ($num_gate_queue != 0)  
   {  
      $gate = pop(@gate_queue);  
      if($gate->{processed}==$gate->{num_inputs}){  
        if($gate->{num_inputs}==2){  
           if(($gate->{input_1}->{level})>($gate->{input_2}->{level})){  
             $gate->{gate_level} = ($gate->{input_1}->{level});  
           }  
           else{  
             $gate->{gate_level} = ($gate->{input_2}->{level});  
           }  
           $gate->{gate_level}++;  
           $gate->{output}->{level}=$gate->{gate_level};  
           unshift(@input_list_struct,$gate->{output});  
           $num_gate_queue--;  
           $num_gates--;  
        }  
        elsif($gate->{num_inputs}==1){  
           $gate->{gate_level} = $gate->{input_1}->{level};  
           $gate->{gate_level}++;  
           $gate->{output}->{level}=$gate->{gate_level};  
           unshift(@input_list_struct,$gate->{output});  
           $num_gate_queue--;  
           $num_gates--;  
        }  
      }  
      else{  
        unshift(@gate_queue,$gate);  
        $num_gate_queue--;  
      }  
   }  
 #the updated levels of the wires are present in input_list_struct  
 #update the fanouts of the gate with the levels from this struct  
   for $gate(@gates){    
      for $inp (@input_list_struct){  
        $inp_test = $inp->{wire_name};  
        if(($gate->{input_1})->{wire_name} =~ m/$inp_test$/){   
           $gate->{input_1}->{level} = $inp->{level};  
        }  
        if($gate->{num_inputs}!=1){  
           if(($gate->{input_2})->{wire_name} =~ m/$inp_test$/){   
             $gate->{input_2}->{level} = $inp->{level};  
           }  
        }  
      }  
   }  
 }  
 print "gate: level\n";  
 for $gate (@gates){  
   print "$gate->{gate_name}: $gate->{gate_level}\n";  
 }  
 print "\n\nPaths and Delays\n";   
 #Path Trace Variable Decl  
 my $wire;  
 my $inp_count = scalar @input_list_struct_2;  
 my $path_count;  
 my @fanout_array;  
 my $path_complete=0;  
 my @path_array;  
 my @tmp_current_path;  
 my $depth=-1;  
 my $tmp_num_fanouts=0;  
 my @num_fanouts;  
 my $num_paths=0;  
 my @saved_restore;  
 my @path_delay;  
 # End path trace variable decl  
 while($inp_count !=0){  
   my @current_path;  
   $wire = pop @input_list_struct_2;  
   $inp_count--;  
   $depth = 0;  
   $num_fanouts[$depth]=1;  
   push @current_path,$wire;  
   $tmp_num_fanouts=0;  
   for $gate (@gates){  
      if(($gate->{input_1})->{wire_name} =~ m/$wire->{wire_name}/){  
        $tmp_num_fanouts++;  
        push @fanout_array,$gate;  
      }  
      elsif($gate->{num_inputs}!=1){  
        if(($gate->{input_2})->{wire_name} =~ m/$wire->{wire_name}/){   
           $tmp_num_fanouts++;  
           push @fanout_array,$gate;  
        }         
      }  
   }       #all fanouts are in the fanout array now pop the fanout array and continue the process  
 #more than 1 fanout need to save the values for future use  
   if($tmp_num_fanouts>1){  
      $depth++;  
      $num_fanouts[$depth] = $tmp_num_fanouts;  
 #save current path for the future  
      my $i=0;  
      for $element (@current_path){  
        $tmp_current_path[$depth][$i]=$element;  
        $i++;  
      }   
      $saved_restore[$depth]=$i;    
   }  
   while((scalar @fanout_array)!=0){  
      $path_complete=0;  
 #pop the next gate in the stack   
      $gate = pop @fanout_array;  
 #when the number of fanouts in the depth is over, reduce the depth  
 #push the new gate in the current path  
      push @current_path,$gate;  
 #trace the wire  
      $wire = $gate->{output};  
      my $flag=0;  
      for my $element2 (@output_list_struct){  
        if($wire->{wire_name} =~ m/$element2->{wire_name}/){  
           $flag = 1;  
        }  
      }  
      if($flag == 0){  
        push @current_path,$wire;  
      }  
      while(!$path_complete){  
 #reached output? path completed  
        for $element (@output_list_struct){  
           if($wire->{wire_name} =~ m/$element->{wire_name}/){  
             $path_complete=1;  
             $num_paths++;  
             push @current_path,$wire;  
             my $j=0;  
             my $i=$num_paths-1;  
             for $element (@current_path){  
                $path_array[$i][$j]=$element;  
                $j++;  
             }    
 #check iteratively if all the previous depth paths are exhausted  
             if($num_fanouts[$depth]>1){  
                $num_fanouts[$depth]--;  
 #resotring current path for a new path   
                my $i=0;  
                splice(@current_path,0);       
                while($i<$saved_restore[$depth]){  
                  for $element ($tmp_current_path[$depth][$i]){  
                     $current_path[$i]=$element;  
                     $i++;  
                  }  
                }  
             }  
             elsif($depth!=0){  
                $depth--;  
 #if the number of fanouts at this depth is greater than 1 then restore else continue with the next cycle  
                while($depth!=0){  
                  if($num_fanouts[$depth]>1){  
 #remove if wrong  
                     $num_fanouts[$depth]--;  
                     my $i=0;  
                     splice(@current_path,0);  
                     while($i<$saved_restore[$depth]){  
                       for $element ($tmp_current_path[$depth][$i]){  
                          $current_path[$i]=$element;  
                          $i++;  
                       }  
                     }  
                     last;  
                  }  
                  else{  
                     $depth--;  
                  }  
                }       
             }  
             last;  
           }  
        }  
 #if path is not completed find fanouts  
        $tmp_num_fanouts=0;  
        if(!$path_complete){  
           for $gate (@gates){  
             if(($gate->{input_1})->{wire_name} =~ m/$wire->{wire_name}/){  
                push @fanout_array,$gate;  
                $tmp_num_fanouts++;  
             }  
             elsif($gate->{num_inputs}!=1){  
                if(($gate->{input_2})->{wire_name} =~ m/$wire->{wire_name}/){   
                  push @fanout_array,$gate;  
                  $tmp_num_fanouts++;  
                }        
             }  
           }#all fanouts are in the fanout array now pop the fanout array and continue the process  
           if($tmp_num_fanouts > 1){  
             $depth++;  
             my $i=0;  
             for $element (@current_path){  
                $tmp_current_path[$depth][$i]=$element;  
                $i++;  
             }    
             $saved_restore[$depth]=$i;    
             $num_fanouts[$depth] = $tmp_num_fanouts;  
           }  
           $gate = pop(@fanout_array);  
           $wire = $gate->{output};  
 #          push @current_path,$wire;  
           push @current_path,$gate;  
        }  
      }  
   }  
 }  
 for(my $i=0;$i<$num_paths;$i++){  
   $path_delay[$i] = 0;  
   for(my $j=0;$j<$#{$path_array[$i]}+1;$j++){  
      if($path_array[$i][$j]->{element} =~ m/gate/){  
        print $path_array[$i][$j]->{gate_name}."->";  
        $path_delay[$i] = $path_delay[$i]+$path_array[$i][$j]->{gate_delay};  
      }  
      elsif($path_array[$i][$j]->{element} =~ m/wire/){  
        print $path_array[$i][$j]->{wire_name}."->";  
        $path_delay[$i] = $path_delay[$i]+$path_array[$i][$j]->{wire_delay};  
      }  
   }  
   print "\t\t delay: ".$path_delay[$i]."\n";  
 }  
Good Luck, Abishek