Wednesday, May 18, 2011

OpenSPARCT1 - Synthesizing only the Instruction Fetch Unit in ISE

In order to study the Instruction Fetch Unit, I thought the RTL schematic view of ISE would be a useful tool. So i collected all the necessary files to synthesize the Instruction Fetch Unit alone of the OpenSPARCT1 core. Here I document the steps


The files that are required for IFU are present in OpenSPARCT1/design/sys/iop/sparc/rtl/Flist.ifu

Xilinx 10.1 is to be used.
Steps
1. Open xilinx10.1
2. create a new project IFU_Sparc
3. Open OpenSPARCT1/design/sys/iop/sparc/rtl/Flist.ifu
4. Add all the files that are specified in the file to the new project
5. Add all the files that are present in design/sys/iop/sparc/ifu/rtl
5. Add all the header files present in /opensparc/design/sys/iop/include
6. Added all the files inside design/sys/common/rtl to the project (simplicity sake)
7. Add all files inside design/sys/srams/ to the project (simplicity sake)
8. Add files OpenSPARCT1/lib/u1.behV and OpenSPARCT1/lib/m1.behV. Rename the files to u1behV.v and m1behV.v so that they are identified as verilog files. make sure they are added to the project

The next step is to set the compile time macros: To do this:
(make sure "sparc_ifu.v" is the top module)
1. Look for the ISE sub-window on the left labeled "Processes"
2. Find the "Synthesize-XST" entry in that window
3. Right click on that entry and select "Properties"
4. In the popup window "Process Properties - Synthesis Options,
select "synthesis options in the left window
5. Set the property display level to "Advanced"
6. In the right list scroll down to find the property
"Verilog Macros"
7. Type the value FPGA_SYN FPGA_SYN_1THREAD FPGA_SYN_NO_SPU FPGA_SYN_8TLB in that box.
8. now DESELCT "process->properties->xilinx specification options->add i/o buffers"
9. Synthesize
10. View RTL schematic.

Error: bw_r_irf_register not found
Find the file bw_r_irf_register in the sources window of ISE
set it as the top module and synthesize
set sparc_ifu.v as the top module and resynthesize

Tuesday, May 17, 2011

LFS - Binutils


INSTALLING BINUTILS package
Shifted to www.linuxfromscratch.org - Linux From Scratch - version 6.8 (the book was outdated so shifting to the website by the same other) - It starts with installation of binutils and not BASH. no problem though.

The main modifications I made is shifted the sources from /usr/src to a dedicated folder at $LFS/sources
The location where the tools are to be installed is $LFS/tools. A symbolic link is created for the same in the host systems

INSTALLATION OF BINUTILS
check for $LFS, $LFS_TGT else
export LFS=/mnt/lfs
export LFS_TGT=$(uname -m)-lfs-linux-gnu

1. download the Binutils-2.21.tar.gz into the $LFS/sources
2. tar xvzf binutils-2.21.tar.gz - extracts into a folder called binutils-2.21
3. mkdir $LFS/sources/binutils-build
4. cd $LFS/binutils-build
5. ../binutils-2.21/confiure --targer=$LFS_TGT --prefix=/tools --disable-nls --disable-werror
6. make
7. make install

LFS_TGT contains the description of the system. The config.guess inside binutils-2.21 contains information on the description of the machine assumed.
--prefix=/tools - tells the configure script to install in the /tools directory
--disable-werror - prevents build from stopping if there are warnings in host compiler

Cannot run the test scripts now because the testsuite framword (Tcl, Expect and DejaGNU is not available yet).

Abishek Ramdas
NYU Poly

LFS - BASH - compilation and installation


DOWNLOADING  REQUIRED PACKAGES
1. Downloading bash - (bash-4.2)
http://ftp.gnu.org/gnu/bash/ - download the latest tar.gz file. I downloaded bash-4.2.tar.gz
It is put inside the folder $LFS/usr/src

* as root (sudo -i) cd into the folder $LFS/usr/src/bash-4.2
* ./configure --enable-static-link --prefix=$LFS/usr --disable-nls --without-bash-malloc
* make

+ERROR: /usr/lib/gcc/i486-linux-gnu/4.4.1/../../../../lib/libc.a(malloc.o): In function `malloc':
(.text+0x4ad0): multiple definition of `malloc'
./lib/malloc/libmalloc.a(malloc.o):/mnt/lfs/usr/src/bash-4.2/lib/malloc/malloc.c:1254: first defined here
+SOLUTION:
./configure --enable-static-link --prefix=$LFS/usr --disable-nls --without-bash-malloc (INCLUDE "--without-bash-malloc") in the configure option.
+REFERENCE:
http://www.linuxforums.org/forum/programming-scripting/129616-multiple-definitions-compliling-error.html
+make succeded

* make prefix=$LFS/usr install
* mv $LFS/usr/bin/bash $LFS/usr/bin/bashbug $LFS/bin
* cd $LFS/bin
* ln -s bash sh


Testing if bash is installed properly
*cd $LFS/bin
*./sh
It should open a new shell which contains information on the version installed. Bash is hence installed successfully.

Abishek Ramdas
NYU Poly

LFS - Creating a partition


These steps are quite straight forward no errors were encountered. Follow the procedure described in
http://www.linuxfromscratch.org/lfs/view/stable/chapter02/chapter02.html

CREATING A PARTITION

I used Gparted tool to create the partition. The tool is quite straight forward to use. You can download it from the package manager. here is the tutorial - http://www.dedoimedo.com/computers/gparted.html

Created a partition using the steps described here
http://www.linuxfromscratch.org/lfs/view/stable/chapter02/creatingpartition.html

Created a partition - 50 GB /dev/sda1 (primary partition)
                        3 GB /dev/sda4 (primary partition for swap)
(note : in my system I have linux (Ubuntu 9.10 karmic koala) installed in logical partition sda5 and swap is in logical parition sda6. primary partition sda2 is extended to create logical partitions.)

MOUTING THE NEW PARTITION

mkdir /mnt/lfs
mount /dev/sda1 /mnt/lfs
export $LFS = /mnt/lfs


CREATING DIRECTORIES
FILE HEIRARCHY STANDARDS : http://www.pathname.com/fhs/
going to root mode in ubuntu - sudo -i
inside /mnt/lfs
create dirctories bin boot dev dev/pts etc home lib mnt proc root sbin tmp var

Create two more folders /usr and /usr/local
inside /usr create bin etc include lib sbin share src tmp var
inside share create following folders dict, doc, info, locale, man, nls, misc, terminfo, zoneinfo
inside share/man, create folders man1 man2 man3 man4 man5 man6 man7 man8
inside the /usr folder create symbolic links to the share/man, share/doc and share/info

inside /usr/local
inside share create following folders dict, doc, info, locale, man, nls, misc, terminfo, zoneinfo
inside share/man, create folders man1 man2 man3 man4 man5 man6 man7 man8
inside the /usr folder create symbolic links to the share/man, share/doc and share/info
(basically repeat the same steps).

Abishek Ramdas
NYU Poly

Building Linux From Scratch

hi,
For long I wanted to build a custom linux system from scratch. Since now I am in my summer hols, I finally find time to do it. I am doing it for a hobby and documenting the procedure I followed, errors that I got and how I have solved them if I have solved them. Hope this documentation serves useful to the people.



IMPORTANT - describes the variables that are used,

1. sudo -i is used to go into the superuser mode in ubuntu
2. $LFS = /mnt/lfs - the partition where linux is being built from scratch is mounted into this location
3. all the packages that are to be installed are to be present in $LFS/usr/src
4. $LFS_TGT=$(uname -m)-lfs-linux-gnu


INDEX
1. Creating a partition
2. Mounting the partition
3. Creating Directories based on the File Hierarchy Standards (FHS)
4. Installing Bash
5. Installing Bin utils

Tuesday, May 3, 2011

READ ME for SOBOL QUASI RANDOM NUMBER GENERATOR

********************************************************************
Quasi Random Number Generator
Abishek Ramdas
********************************************************************
Single threaded implementation
File name - quasi_rand_gen_modification.c

How to run -
at the command prompt

$gcc quasi_rand_gen_modification.c (return)
$./a.out (return)

Output:
Requests:  Number of patterns to be generated and Dimensions
File - QRNG_Patterns_sngl_thrd.txt in the same folder which contains the C file.

********************************************************************
Multiple threaded implementation
File name - quasi_rand_gen_pthreads.c

How to run -
at the command prompt

$gcc -pthread quasi_rand_gen_modification.c (return)
$./a.out (return)

Output:
Requests:  Number of patterns to be generated, Dimensions and Number of cores
File - QRNG_Patterns_pthreads.txt in the same folder which contains the C
file.

********************************************************************
Testing Driver

In the linux system there is a binary called diff

Usage : diff filename1 filename2 (return)

Result : gives the differnce between the two files. gives no output if the two files are the same.

syntax
$diff QRNG_Patterns_sngl_thrd.txt QRNG_Patterns_pthreads.txt

*********************************************************************
Additional information
1. Make sure the number the same number of patterns are generated for single threaded and multi threaded version.
2. Make sure the dimensions provided are also the same.
3. A sleep signal is provided for 2 seconds before the output is printed on the screen in the multi threaded part. so if it looks like it hanged please wait.
********************************************************************

Sobol Quasi Random Number Generator single thread version

#include<stdio.h>
#include<stdlib.h>
#include<error.h>
#include<errno.h>
#include"nrutil.h"

#define MAXBIT 30
#define MAXDIM 6
#define DEBUG 1

void sobseq(int *, float []);

int main(int argc, char *argv[])
{
  int n,i;
  float x[100];
  for(i=0;i<100;i++)
    x[i]=0;
  n=-1;
  sobseq(&n,x);
  //  for(i=0;i<100;i++)
  //  printf("%f",x[i]);
  n=4;
  sobseq(&n,x);
  for(i=0;i<100;i++)
    printf("%f\n",x[i]);
 n=5;
  sobseq(&n,x);
  for(i=0;i<100;i++)
    printf("%f\n",x[i]);
  return 0;
}

void sobseq(int *n,float x[])
{
  int j,k,l;
  unsigned long i,im,ipp;
  static float fac;
  static unsigned long in,ix[MAXDIM+1],*iu[MAXBIT+1];
  static unsigned long mdeg[MAXDIM+1]={0,1,2,3,3,4,4};
  static unsigned long ip[MAXDIM+1]={0,0,1,1,2,1,4};
  static unsigned long iv[MAXDIM*MAXBIT+1]={0,1,1,1,1,1,1,3,1,3,3,1,1,5,7,7,3,3,5,15,11,5,15,13,9};
  printf("n = %d\n",*n);
  if(*n<0)
    {
      for(k=1;k<=MAXDIM;k++) ix[k]=0;
      in=0;
      if (iv[1] != 1) return;
      fac=1.0/(1L << MAXBIT);
      if(DEBUG)
    {
      printf("debug:\n");
      printf("n: %d\n",*n);
      printf("fac: %1.30f\n",fac);
      printf("1L: %ld\n",1L);
      printf("end debug\n");
    }
      for (j=1,k=0;j<=MAXBIT;j++,k+=MAXDIM)
    {
      //iu is array of arrays. contains the address of each element of array iv
      //initialization iu so that addresses of iv are loaded in to iu
      iu[j] = &iv[k];
      if(DEBUG)
        {
          printf("j= %d,k = %d:\t%ld\n",j,k,*iu[j]);
        }
    }
      for (k=1;k<=MAXDIM;k++)
    {
      for (j=1;j<=mdeg[k];j++)
        {
          if(DEBUG)
        {
          printf("mdeg = %ld\n",mdeg[k]);
          printf("iu[%d][%d] = %ld\n",j,k,iu[j][k]);
          printf("(maxbit-%d) = %d\n",j,(MAXBIT-j));
        }
          //initialize vi values
          iu[j][k] <<= (MAXBIT-j);
          if(DEBUG)
        {
          printf("iu[%d][%d] = %ld\n",j,k,iu[j][k]);
          printf("(maxbit-%d) = %d\n",j,(MAXBIT-j));
        }
          printf("\n");
        }
      for(j=mdeg[k]+1;j<=MAXBIT;j++)
        {
          ipp=ip[k];
          i=iu[j-mdeg[k]][k];
          i ^= (i >> mdeg[k]);
          for (l=mdeg[k]-1;l>=1;l--)
        {
          if (ipp & 1) i ^= iu[j-l][k];
          ipp >>= 1;
        }
          iu[j][k]=i;
          printf("iu[%d][%d]: %f\n",j,k,iu[j][k]*fac);
        }
    }
    }
  else
    {
      printf("inside else\n ");
      im=in++;
      for(j=1;j<=MAXBIT;j++)
    {
      if (!(im & 1)) break;
      im >>= 1;
    }
      if (j > MAXBIT) error(1,errno,"MAXBIT too small in sobseq");
      im=(j-1)*MAXDIM;
      printf("IMIN %d\n",IMIN(*n,MAXDIM));
      for(k=1;k<=IMIN(*n,MAXDIM);k++)
    {
      ix[k] ^= iv[im+k];
      x[k]=ix[k]*fac;
      if(DEBUG)
        {
          printf("x[%d] : %f\n",k,x[k]);
          printf("fac : %1.30f\n",fac);
          printf("iv[%ld] : %ld\n",im+k,iv[im+k]);
        }
    }
    }
}

Parallelized Sobol Quasi Random Number Generator using Pthreads

/*
********************************************************************
Quasi Random Number Generator - serial version
Abishek Ramdas
********************************************************************
Inputs :
1. Number of patterns (limit 64000) can be varied by varying the LIM paramter
2. Number of dimensions

Outputs:
All patterns are stored in file QRNG_Patterns_sngl_thrd.txt
the patterns are printed along the x axis and the dimensions are along y axis
********************************************************************
*/


#include<stdio.h>
#include<stdlib.h>
#include<error.h>
#include<errno.h>
#include"nrutil.h"


#define LIM 64000 //limitng the number of patterns generated to max of 64000
#define MAXBIT 30
#define MAXDIM 6
#define DEBUG_INIT 0
#define DEBUG_SEED 0
#define DEBUG_SOBOL 0
#define DEBUG_SOBOL_E 0

float random_numbers[MAXDIM][LIM];//dynamic declaration of 2D array is not possible

int main(int argc, char *argv[])
{
  int loop,init=1;
  unsigned long in_G,in_temp,no_of_vectors;
  int dim;//number of values to be generated
  int *n = &dim;
  float x[6];
  char filename[]="QRNG_Patterns_sngl_thrd.txt";//file contains patterns for a single threaded execution
  FILE *fp;
  fp=fopen(filename,"w");

  //  no_of_vectors = 20;

  int j,k,l;
  unsigned long i,im,ipp;
  static float fac;
  //  static unsigned long in,ix[MAXDIM+1],*iu[MAXBIT+1];
  unsigned long in,ix[MAXDIM+1],*iu[MAXBIT+1];
  static unsigned long mdeg[MAXDIM+1]={0,1,2,3,3,4,4};
  static unsigned long ip[MAXDIM+1]={0,0,1,1,2,1,4};
  static unsigned long iv[MAXDIM*MAXBIT+1]={0,1,1,1,1,1,1,3,1,3,3,1,1,5,7,7,3,3,5,15,11,5,15,13,9};

  printf("Enter the number of vectors required:");
  scanf("%ld",&no_of_vectors);
  printf("Enter the dimensions:");
  scanf("%d",n);
  printf("single threaded version\n");
  if(init==1)
    {
      //      printf("initializing... \n");
      for(k=1;k<=MAXDIM;k++) ix[k]=0;
      in=0;
      if (iv[1] != 1) return;
      fac=1.0/(1L << MAXBIT);
      if(DEBUG_INIT)
    {
      printf("debug:\n");
      printf("n: %d\n",*n);
      printf("fac: %1.30f\n",fac);
      printf("1L: %ld\n",1L);
      printf("end debug\n");
    }
      for (j=1,k=0;j<=MAXBIT;j++,k+=MAXDIM)
    {
      //iu is array of arrays. contains the address of each element of array iv
      //initialization iu so that addresses of iv are loaded in to iu
      iu[j] = &iv[k];
      if(DEBUG_INIT)
        {
          printf("j= %d,k = %d:\t%ld\n",j,k,*iu[j]);
        }
    }
      for (k=1;k<=MAXDIM;k++)
    {
      for (j=1;j<=mdeg[k];j++)
        {
          if(DEBUG_INIT)
        {
          printf("mdeg = %ld\n",mdeg[k]);
          printf("iu[%d][%d] = %ld\n",j,k,iu[j][k]);
          printf("(maxbit-%d) = %d\n",j,(MAXBIT-j));
        }
          //initialize vi values
          iu[j][k] <<= (MAXBIT-j);
          if(DEBUG_INIT)
        {
          printf("iu[%d][%d] = %ld\n",j,k,iu[j][k]);
          printf("(maxbit-%d) = %d\n",j,(MAXBIT-j));
        }
        }
      for(j=mdeg[k]+1;j<=MAXBIT;j++)
        {
          ipp=ip[k];
          i=iu[j-mdeg[k]][k];
          i ^= (i >> mdeg[k]);
          for (l=mdeg[k]-1;l>=1;l--)
        {
          if (ipp & 1) i ^= iu[j-l][k];
          ipp >>= 1;
        }
          iu[j][k]=i;
        }
    }
    }
 
  //Generate SEED for a particular index of random number
  in = -1;//in - index of (n-1)random number
  im = in++;
  in_G=in;
  in_temp = in;
  in_temp >>= 1;
  in_G ^= in_temp;
  if(DEBUG_SEED)
    {
      printf("Random # index : %ld\n",in);
      printf("Random # index in Gray in_G : %ld\n",in_G);
      printf("Generating random numbers from index: %ld\n",in+1);
    }
  for(k=1;k<=IMIN(*n,MAXDIM);k++)
    {
      in_G=in;
      in_temp = in;
      in_temp >>= 1;
      in_G ^= in_temp;
      if(DEBUG_SEED)
    {
      printf("ix[%d] =",k);
    }

      for(loop=0;loop*MAXDIM<(MAXBIT*MAXDIM+1);loop++)
    {
      //if LSB in in_G =0 then dont xor else xor
      if((in_G&1))
        {
          ix[k]^=iv[k+(loop*MAXDIM)];
          in_G >>= 1;
           if(DEBUG_SEED)
        {
          printf("iv[%d+%d]^",k,loop*MAXDIM);
        }
        }
      else
        {
          in_G >>= 1;
        }
    }
      if(DEBUG_SEED)
    {
      printf("\nseed value for rand #%ld : ix[%d]=%ld",in,k,ix[k]);
      printf("\n");
    }
    }

  //SEED is generated
  //Generate the random numbers next

  for(i=0;i<no_of_vectors;i++)//i is the number of random numbers to be generated
    {
      im=in++;
      if(DEBUG_SOBOL_E)
    {
      printf("in=%ld\n",in);
      printf("im=%ld\n",im);
    }
      for(j=1;j<=MAXBIT;j++)
    {
      if (!(im & 1)) break; //identify the location of the right most 0 in im. it is indicated by j
      im >>= 1;
      if(DEBUG_SOBOL_E)
        {
          printf("im2=%ld\n",im);
        }
    }
      if (j > MAXBIT) error(1,errno,"MAXBIT too small in sobseq");
      im=(j-1)*MAXDIM;
      if(DEBUG_SOBOL_E)
    {
      printf("j : %d\n",j);
      printf("im3=%ld\n",im);
      printf("IMIN %d\n",IMIN(*n,MAXDIM));
    }
     
      for(k=1;k<=IMIN(*n,MAXDIM);k++)
    {
      if(DEBUG_SOBOL)
        printf("ix[%d] = %ld\n",k,ix[k]);

      ix[k] ^= iv[im+k];
      x[k]=ix[k]*fac;
      random_numbers[k-1][i]=x[k];
      if(DEBUG_SOBOL)
        {
          printf("ix[%d]^= iv[%ld] => %ld ^= %ld => %f\t",k,im+k,ix[k],iv[im+k],x[k]);
      //          printf("fac : %1.30f\n",fac);
      //          printf("iv[%ld] : %ld\n",im+k,iv[im+k]);
        }

      if(!DEBUG_SOBOL)
        {
          printf("%f  ",x[k]);
        }
    }
      printf("\n");
     
    }
    printf("\nFinal Result\n");
  for(k=0;k<IMIN(*n,MAXDIM);k++)
    {
      for(i=0;i<no_of_vectors;i++)
    {
      //  printf("%f  ",random_numbers[k][i]);
      fprintf(fp,"%f  ",random_numbers[k][i]);//%f2spaces
    }
      fprintf(fp,"\n");
      //      printf("\n");
    }
  fclose(fp);
  printf("Random Numbers are stored in ./%s\n",filename);
  return 0;
}

SOC Encounter for layout generation

The netlist for the interfaced design is available. This is to be ported into SOC encounter to generate a layout.

Design methodology – top down

The design is synthesized so as to define the components in standard cells of the OSU 25 library. This synthesized netlist is imported to encounter to generate the layout.

The Steps for chip planning in Encounter are
1.Import netlist
2.Floor plan
3.Create a black box partition of the memory
4.Power planning
5.specify modules and black boxes position on the chip
6.special route
7.Run placement
8.Assign pins for the black box
9.Run trial route – analyze for congestion
10.Run nano route

1. IMPORT NETLIST
    The synthesized netlist is imported into encounter and the osu25_stdcells.lef and osu25_stdcells.tlf libraries are mapped. The power nets and ground nets are specified to be “vdd” and “gnd”.

2. FLOOR  PLANNING
The sizes of the individual modules were measured for a total utilization of 70%. A memory generator was used to generate the 256 byte memory. The size was measured and all the modules were incorporated in the floor plan. The memory is a black box partition.

3. POWER PLANNING

1.Connecting Global nets - The global vdd and gnd pins are connected.
2.Power ring is added around the die - Metal 5 and Metal 4 of width 8 and spacing 1 with an offset of 1 are used.
3.Power stripes are added - Metal 5 is used for power stripes

4. SPECIAL ROUTE
The pad pins are deselected. Top layer is selected as metal 5 and bottom layer is metal1.

5. PLACEMENT
The standard cells are placed followed by filler cells to remove possible DRC errors. The back box offers a placement blockage and hence no cells are placed inside the region.

The placed design with the memory black box is shown here.


6. TRIAL ROUTE
Trial route is done to analyze congestion. The trial route for the chip is as shown below
As seen in the diagram, there are no congestion markers and hence no congestion in the floor plan.

7. PIN ASSIGNMENT
The pins are assigned for the black box in positions that are suitable for easy connection in Virtuso. It is seen in the trial route that wires pass through the memory black box which might result in DRC errors. Hence these pins are also moved to locations that are advantageous in terms of routing.

8. NANO ROUTING
After pin assignment is done, Nano routing is done. The nano routed design is saved as a GDS file. This file is used to port the design into Virtuoso.


In virtuso a new library called Open8_MEM_Motor is created. The memory is generated inside this library with the cell name same as the VHDL description of the RAM using the generatememory procedure. The memory has 8 address lines 8 data lines, 1 read/write_bar control lines. These are to be connected to the pins that are described in encounter.


Connections from the pins assigned are made to the data/ control pins of the memory that is generated. There was a small problem with the lines from the row decoder of the memory. The row decoders are also to be modified in virtuso.


Again there was no DRC errors but LVS failed to pass.

Abishek Ramdas
NYU Poly

Interfaced Design

This post is about interfacing all the modules of the obstacle avoidance project and optimization techniques.

The design is inter connected in the HDL description itself. The memory is defined as a black box. A black box in VHDL is an entity without an architecture. Since the memory is to be added later, it is described as a black box. The VHDL files for the interfaced design is sourced into the RTL compiler.
As you can see, a lock to the side of the memory module. This shows that the memory is a black box. The netlist is generated for this design using RTL Compiler.

The next step is verification of this netlist. But since the memory is not available, it cannot be tested.

DESIRED FREQUENCY OF OPERATION
The desired frequency of operation was set to 0.5 GHz (2000 ps). The clock was set to this requency using the set clock command of RTL compiler. The worst negative slack is calculated.
 It is seen that for a frequency of 0.5 GHz, the worst negative slack is -1406 ps and hence the circuit is operating at a frequency lesser than the intended frequency. this calls for optimization. I applied the retiming optimization to reduce the slack.


set_attribute retiming true /design/Open8_MEM_Motor/


This retimes the circuit to rearrange the flipflops to reduce the worst negative slack. The WNS is decreased to -1084 ps through retiming. The working frequency for this WNS is 0.3 GHz which was considered fine because response form the motors are going to be slower when compared to speed of operation of the circuit.
Thus the frequency of operation of the interfaced design is 0.3GHz.

Synthesis of the Motor Controller

The Flow of Asic design is

1. RTL Description
2. Simulation and testing of functionality
3. Synthesis of netlist using RTL Compiler
4. Verification of resultant netlist

The HDL Description of the motor controller is available. The next step is to synthesize it to a netlist made up of the standard cells.

The library used is the osu025_stdcells.lib

The HDL files for the motor controller are read by the RTL Compiler. The following lines are added to a tcl file which is then sourced from the RTL Compiler

File : rtl.tcl

set_attribute lib_search_path /path_to/cadence/local/osu_soc_v2.7/cadence/lib/tsmc025/signalstorm
read_hdl -vhdl  ../HDL/motor_controller.vhd (location of motor controller)
elaborate
synthesize -to_mapped
write -mapped > motor_controller.v
write_script > script

This script was edited and sourced in the RTL compiler to synthesize the motor controller for verification. Note: no optimization parameters are specified.



as you can see the synthesis should succeed without errors. The resultant netlist is available in motor_controller.v. The next step is verification of the functionality of the netlist. This is done by porting the netlist to a schematic version in spectre and simulation using analog environment.

The netlist is imported to encounter and after generating a placed and routed layout without violations, it is saved as a gds2 file. The detailed procedure is given HERE

The GDS2 is ported into ICFB using a script provided by cadence and the schematic view is generated.


The schematic is simulated using the analog environment for verifying the netlist. The method of simulation done was load a control word into the motor controller and see the output. The control word loaded is 00110011 which means both the motors are moved forward by 3 steps, The waveforms are as follows


It can be seen that indeed both the motors shift in the right direction for 3 steps after which the control word is again loaded in by the user. The netlist is verified to be functionally correct. But the LVS do not match.

One main reason DRC fails is because of presence of labels for pins. Deleting the labels for the pins removed all DRC errors. LVS still failed to match. Was not able to look into the reasons for the want of time.

Abishek Ramdas
NYU Poly