Tuesday, May 3, 2011

Interfaced Design

This post is about interfacing all the modules of the obstacle avoidance project and optimization techniques.

The design is inter connected in the HDL description itself. The memory is defined as a black box. A black box in VHDL is an entity without an architecture. Since the memory is to be added later, it is described as a black box. The VHDL files for the interfaced design is sourced into the RTL compiler.
As you can see, a lock to the side of the memory module. This shows that the memory is a black box. The netlist is generated for this design using RTL Compiler.

The next step is verification of this netlist. But since the memory is not available, it cannot be tested.

The desired frequency of operation was set to 0.5 GHz (2000 ps). The clock was set to this requency using the set clock command of RTL compiler. The worst negative slack is calculated.
 It is seen that for a frequency of 0.5 GHz, the worst negative slack is -1406 ps and hence the circuit is operating at a frequency lesser than the intended frequency. this calls for optimization. I applied the retiming optimization to reduce the slack.

set_attribute retiming true /design/Open8_MEM_Motor/

This retimes the circuit to rearrange the flipflops to reduce the worst negative slack. The WNS is decreased to -1084 ps through retiming. The working frequency for this WNS is 0.3 GHz which was considered fine because response form the motors are going to be slower when compared to speed of operation of the circuit.
Thus the frequency of operation of the interfaced design is 0.3GHz.

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