Tuesday, May 3, 2011

SOC Encounter for layout generation

The netlist for the interfaced design is available. This is to be ported into SOC encounter to generate a layout.

Design methodology – top down

The design is synthesized so as to define the components in standard cells of the OSU 25 library. This synthesized netlist is imported to encounter to generate the layout.

The Steps for chip planning in Encounter are
1.Import netlist
2.Floor plan
3.Create a black box partition of the memory
4.Power planning
5.specify modules and black boxes position on the chip
6.special route
7.Run placement
8.Assign pins for the black box
9.Run trial route – analyze for congestion
10.Run nano route

    The synthesized netlist is imported into encounter and the osu25_stdcells.lef and osu25_stdcells.tlf libraries are mapped. The power nets and ground nets are specified to be “vdd” and “gnd”.

The sizes of the individual modules were measured for a total utilization of 70%. A memory generator was used to generate the 256 byte memory. The size was measured and all the modules were incorporated in the floor plan. The memory is a black box partition.


1.Connecting Global nets - The global vdd and gnd pins are connected.
2.Power ring is added around the die - Metal 5 and Metal 4 of width 8 and spacing 1 with an offset of 1 are used.
3.Power stripes are added - Metal 5 is used for power stripes

The pad pins are deselected. Top layer is selected as metal 5 and bottom layer is metal1.

The standard cells are placed followed by filler cells to remove possible DRC errors. The back box offers a placement blockage and hence no cells are placed inside the region.

The placed design with the memory black box is shown here.

Trial route is done to analyze congestion. The trial route for the chip is as shown below
As seen in the diagram, there are no congestion markers and hence no congestion in the floor plan.

The pins are assigned for the black box in positions that are suitable for easy connection in Virtuso. It is seen in the trial route that wires pass through the memory black box which might result in DRC errors. Hence these pins are also moved to locations that are advantageous in terms of routing.

After pin assignment is done, Nano routing is done. The nano routed design is saved as a GDS file. This file is used to port the design into Virtuoso.

In virtuso a new library called Open8_MEM_Motor is created. The memory is generated inside this library with the cell name same as the VHDL description of the RAM using the generatememory procedure. The memory has 8 address lines 8 data lines, 1 read/write_bar control lines. These are to be connected to the pins that are described in encounter.

Connections from the pins assigned are made to the data/ control pins of the memory that is generated. There was a small problem with the lines from the row decoder of the memory. The row decoders are also to be modified in virtuso.

Again there was no DRC errors but LVS failed to pass.

Abishek Ramdas
NYU Poly

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