The instruction ROM is an IP Core. so before interfacing with the open8, it has to be generated. The method of generating and simulating a ROM Xilinx IP Core is described here.
FIND ALL THE FILES HERE
1. app.coe (the initialization file)
Creation of the ROM
1. open ISE
2. create a new project
3. tools -> core generator(12.1) (or right click on the device and add a new file 10.1)
4. In the IP catalog -> Memory and storage elements -> RAM and ROM
5. double click on block memory generator, A new window opens
6. In the new window select single port ROM click next, Write first mode
Read Width = 8 and Read Depth = 16384 for 16K ROM -> next
8. The output ports are unregistered, load initialization COE if required -> next
9. No need to use the Reset pin -> next
10. Generate. (takes a little time then shows successfully generated)
This generated ROM has to be connected to the Open8 and functions as the program memory. The ROM provides a VHDL file. needs to be connected to the open8
Simulation using Modelsim
1. The ip core is generated in the ipcore_dir directory inside the current project
2. The most important files are the .vhd, .xco,.vho, .mif
3. Simulate the .vhd file as any other vhdl file. copy the .xco file into the simulation directory and the .vho contains information on how to instantiate the ip core
The simulation directory contains .vhd,.vho,.xco,.mif
4. For simulation it is essential that you compile the xilinx libraries namely unisim, simprim and xilinxcorelib.(mainly xilinxcorelib because it contains the definition for the ipcore).
5. Write a top level that instantiates the memory as a component and write a test bench to test the memory created
ERROR: Error: Could not find xilinxcorelib.blk_mem_gen_v7_2.
Make sure you have compiled the xilinx libraries unisim, simprim and xilinxcorelib in modelsim.