Poly SPARC

The instruction ROM is an IP Core. so before interfacing with the open8, it has to be generated. The method of generating and simulating a ROM Xilinx IP Core is described here. FIND ALL THE FILES HERE 1. app.coe (the initialization file) 2. rom_16k_core.vhd 3. rom_16k_core.vho 4. rom_16k_core.xco 5. top_level.vhd 6. do_memgen.do Creation of the ROM Xilinx 10.1 1. open ISE 2. create a new project 3. tools -> core generator(12.1) (or right click on the device and add a new file 10.1) 4. In the IP catalog -> Memory and storage elements -> RAM and ROM 5. double click on block memory generator, A new window opens 6. In the new window select single port ROM click next, Write first mode 7. Select Read Width = 8 and Read Depth = 16384 for 16K ROM -> next 8. The output ports are unregistered, load initialization COE if required -> next 9. No need to use the Reset pin -> next 10. Generate. (takes a little time then shows successfully generated) This

Hi, There was a misunderstanding regarding to the bug I had encountered while using open 8 core. The bug is that there was a displacement of 1 cycle in the processor code while fetching the return address executing the "RTI" instruction. It is described in detail here . This is not actually a bug because the processor was pipelined in such a way that the data was to be read from the memory in a span of 2 cycles while my assumption about the memory model was that data was fetched in 1 cycle. This pipelining was done in order to increase the frequency of operation. So the memory model is described as follows - 16 k single ported ROM in the write first mode. width = 8 and depth = 16k (16384). The pipeline operation is described here as a stand alone project. (not connected to the open8) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity rom_16k is port(   Clock                 : in  std_logic;   --