Poly SPARC

OpenSPARCT1 comes with a built in script called rsyn that is used to synthesize the required verilog files using synopsys design compiler. All the modules are individually compiled (except the mega cells) and you get the flattened and hierarchical verilog netlist file for individual modules.  You do not have the netlist file for the entire OpenSPARCT1 yet and that has to be done manually.   Important Scripts provided by SUN The OpenSPARCT1/design/sys/synopsys/script folder contains the scripts to configure and run synopsys   There are two configuration files     1. io configuration - project_io_cfg.scr     2. sparc configuration - project_sparc_cfg.scr  they contain the configuration information. Rsyn flow The rsyn command calls identifies the tool that is to be used and then calls the "rsyn,1.0" file in OpenSPARCT1/tools/perlmod 1. The rsyn file reads the block list that is present in OpenSPARCT1/design/sys/synopsys/. 2. It run...

It would be required to synthesize individual blocks in SPARC separately. For example, the method to synthesize the Load Store Unit is described here. You need to have successfully run rsyn - how? example lsu unit present in design/sys/iop/sparc/lsu Steps 1. Create a work folder anywhere you like 2. cd into design/sys/iop/sparc/lsu 3. Use the following script to collect the flat_files from the location 4. Use the following script to extract the flat nestlist from all modules inside lsu to a folder called flat_files Script: file_collect.sh (location /design/sys/iop/sparc/lsu) cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu/flat_files done 5. copy the files that are present in ...

--> You need to have successfully run rsyn - how? Sparc has a number of blocks. bw_clk_cl_sparc_cmp cpx_spc_buf cpx_spc_rpt exu ffu ifu lsu mul spu tlu spc_pcx_buf    Steps are 1. collect all the flattened netlist files from each block in work folder file_collect.sh - location design/sys/iop/sparc cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/ for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files done cd design/sys/iop/sparc mkdir flat_files ./file_collect.sh All the flat files in the sparc folder are present in /design/sys/iop/sparc/flat_files 2. collect the top level files from each of the blocks you will find the top level blocks for each module in the rtl folder inside that module current fldr - design/sys...

If we are required to find area information or the routing information of the entire processor (with all 8 cores etc) we have to manually compile the flattened netlist file with the top level file of the processor. The procedure is described here. The top level module for OpenSPARCT1 is “iop.v” located at design/sys/iop/rtl Synthesize the whole processor using design vision I need the area information of the processor with all 8 cores 1. Run rsyn to generate all the flattened netlist - how? 2. collect all the flattened netlist file in a folder File: file_collect.sh Location ~/opt/OpenSPARCT1/flat_files cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files done 3. The top level file for the entire OpenSPARC chip is present in design/sy...

Configuration file for design_vision # synopsys_dc.setup file for opensparc # Define the lsi_10k library set SYN_LIBS /opt/synopsys/syn/libraries/syn set SPARC_INC /home/ar2654/opt/OpenSPARCT1/design/sys/iop/include # Define the libraries and search path set search_path [concat $search_path ${SYN_LIBS} ${SPARC_INC}] set target_library ${SYN_LIBS}/lsi_10k.db set link_library [concat "*" $target_library] set symbol_library ${SYN_LIBS}/lsi_10k.sdb define_design_lib WORK -path home/ar2654/opt/OpenSPARCT1/SYN_full/WORKar2654@nanovlsi % File: file_collect.sh cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files done

  rsyn compiles all the files using design compiler. The default library used is lsi_10k.db Open Design and verification guide In the quick start section 1.3.1 follow unzip and untar commands cd to the folder untared Open the OpenSPARC.cshrc script Edit the document to set up the environment for openSPARC.cshrc synopsys libraries - /opt/synopsys/syn sparcos5 libraries - I was not able to find the libraries at the place mentioned in the document so I used to locate command to locate sparcos5 libraries locate sparcOS5 source the .tcshrc_synopsys file (it contains the license file in my case) source OpenSPARCT1.cshrc file rsyn -all If everything runs well you can find In the folder of every component (analog/*, ccx/* etc) you can find a folder called synopsys Inside that folder you will have log files for commands and design compiler A gate folder which contains the compiled, flattened and hierarchical ne...

# User needs to define these new variables setenv DV_ROOT /home/location_to/OpenSPARCT1 setenv MODEL_DIR /home/location_to/OpenSPARCT1_model if (`uname -s` == "SunOS") then setenv CC_BIN "/usr/dist/pkgs/sunstudio_`uname -p`/SUNWspro/bin" else setenv CC_BIN /usr/bin endif # Please define VERA_HOME only if you have VERA, otherwise comment it out. if ((`uname -s` == "SunOS") && (`uname -p` == "sparc")) then # setenv VERA_HOME /import/EDAtools/vera/vera,v6.2.10/5.x else # setenv VERA_HOME endif # Please define VCS_HOME only if you have VCS, otherwise comment it out. #setenv VCS_HOME /import/EDAtools/vcs/vcs7.1.1R21 # Please define NCV_HOME only if you have NC-Verilog, otherwise comment it out. #setenv NCV_HOME /import/EDAtools/ncverilog/ncverilog.v5.3.s2/5.x # Please define NOVAS_HOME only if you have Debussy, otherwise comment it out. if ((`uname -s` == "SunOS") && (`uname -p` == "sparc"))...

In order to study the Instruction Fetch Unit, I thought the RTL schematic view of ISE would be a useful tool. So i collected all the necessary files to synthesize the Instruction Fetch Unit alone of the OpenSPARCT1 core. Here I document the steps The files that are required for IFU are present in OpenSPARCT1/design/sys/iop/sparc/rtl/Flist.ifu Xilinx 10.1 is to be used. Steps 1. Open xilinx10.1 2. create a new project IFU_Sparc 3. Open OpenSPARCT1/design/sys/iop/sparc/rtl/Flist.ifu 4. Add all the files that are specified in the file to the new project 5. Add all the files that are present in design/sys/iop/sparc/ifu/rtl 5. Add all the header files present in /opensparc/design/sys/iop/include 6. Added all the files inside design/sys/common/rtl to the project (simplicity sake) 7. Add all files inside design/sys/srams/ to the project (simplicity sake) 8. Add files OpenSPARCT1/lib/u1.behV and OpenSPARCT1/lib/m1.behV. Rename the files to u1behV.v and m1behV.v so that they are ...

Running a system level simulation of OpenSPARCT1 with ModelSIM Simulation of the opensparc is very important if you are going to understand its inner details. System level Simulation steps are given in the Design and verification guide chapter 6.7. The flow is to compile the libraries requried for simulation in ModelSIM and let the simulation scripts provided by the sparc people take care of simulating the system. Two sets of libraries are to be compiled. One for the ISE and the other for the EDK in the same order. The system requirements are Requirements ModelSIM SE/PE v6.5 is required to simulate XPS - 10.1.03 is required- If you have xilinx 10.1 to update it to 10.1.03 1. open xps 2. help -> about 3. If version is 10.1 4. help -> xilinx update 5. if version is 10.1.03 then you are allset RAM > 1.5 GB Compiling the libraries for modelsim in ISE source xilinx env variables source modelsim env variables 1. open a new project in ISE 2. Choose the device and...

MODELSIM - simulation of the sparc single core STEPS TO DO 1. create a working directory 2. open modelsim and create a library inside the working directory 3. after creating library open modelsim.ini file in an editor 4. search for Voptflow variable and change its value to 0 (Voptflow = 0) 5. add all the files inside OpenSPARCT1/design/sys/iop/sparc/xst/sparc.flist into the working directory 6. add all header files from the Opensparc/design/sys/iop/include into this folder 7. vlog *.v 8. vsim sparc.v The test benches are not known. I am in the process of identifying the test bench. :) Thought would dig into the EDK project into the MicroBlaze. One hell of a plan.

A. Running the regression.  Using NC Verilog simulator. core1_full regression. The core1 environment consists of one SPARC CPU core. 1. Download the OpenSPARCT1.tar.bz2 to the directory "/home/abishek/OpenSPARCT1" folder. 2. unzip and extract in the same folder 3. Set following environment variables in OpenSPARCT1.bash. comment out the rest DV_ROOT=/home/abishek/OpenSPARCT1 MODEL_DIR=/home/abishek/OpenSPARCT1_model (create the folder specified by the path represented by MODEL_DIR variable.} CC_BIN=/usr/bin (if not running in solaris system) NCV_HOME=/import/EDAtools/ncverilog/ncverilog.v5.3.s2/5.x (default path. change if required to change depending on the installation of NCverilog) LM_LICENSE_FILE="/import/EDAtools/licenses/ncverilog_key" (LM_LICENSE_FILE="/import/EDAtools/licenses/synopsys_key:/import/EDAtools/licenses/ncverilog_key") PERL_CMD="/usr/bin/perl" (if not running in solaris system) PATH= (include onl...

How to synthesize sparc.ngc (openSPARCT1) using Xilinx ISE IDE use Xilinx 10.1. compatibility issues witn Xilinx 12.2 The procedure was discussed by "formal guy" from the xilinx forum. But there were a few more parameters that needed to be set so that Open Sparc can be synthesized using the ISE. The method described below is tested. Here is a little more information on how to synthesize the T1 core manually from the ISE GUI. This is the procedure to follow if you can't use our automated scripts rsynp and rxil. (For exampe if you are on a Windows machine). From the start menu, select ISE -> Project Navigator From the Project Navigator GUI, select File->New Project ( the new project wizard may come up automatically if it is the first time you are running Project Navigator Select a project name and the project path Click next The next window is Device Properties: Select the correct Device, Package, and speed grade for your board. Click next The next w...

Here I briefly describe the documents that are important if you are starting with opensparc for the first time. I have added the description of the important folders.  If you are trying to do synthesis, regression, diag tests read the OpenSPARC DV GUIDE . Most important resource. IMPORTANT DOCUMENTS IN THE RUNNING OF RXIL     1. README: file :This file must be read initially and specifies the values to the environment variables that are to be sourced.     2. OpenSPARCT1.bash (or) OpenSPARCT1.csh : script : are the scripts where the environment variables are actually initialized. Depending on your shell, one of these files are modified and sourced.     3. Xilinx12.1.sh: script :This script is used to initialize the locations of the xilinx tools that are required to run rxil and create NGC and V files. Commnet out lines that are not required by you.     4. Rxil: script : it is a script that check the env variables se...

RXIL 1.# PERL SCRIPT FLOW OF CONTROL by Abishek Ramdas NYU Poly SYNOPSYS          The RXIL1.2 version of the perl script is described here. This perl script is invoked by the rxil command followed by paramenters for xilinx synthesis. Visit the design and verification guide for details on running the rxil command for xilinx.      The rxil command is located inside OpenSPARCT1/tools/bin/rxil. It is a bash script. There are different versions of rxil (perl script) if you look inside OpenSPARCT1/tools/perlmod/ (ex rxil,1.0 ,rxil,1.1 ,rxil,1.2). rxil bash script is used to find the latest version of rxil perl script and transfer control to that script. This bash script calls the  configsrch script to searcg for the latest configuration of rxil. ( it executes configsrch rxil /). It is also used to identify the machine and set the environment variable PERL5OPT according to the machine. This script then calls the current ver...