Saturday, March 5, 2011

OpenSPARC Regression on NC Verilog, ModelSIM

A. Running the regression. 
Using NC Verilog simulator. core1_full regression. The core1 environment consists of one SPARC CPU core.

1. Download the OpenSPARCT1.tar.bz2 to the directory "/home/abishek/OpenSPARCT1" folder.

2. unzip and extract in the same folder

3. Set following environment variables in OpenSPARCT1.bash. comment out the rest

DV_ROOT=/home/abishek/OpenSPARCT1
MODEL_DIR=/home/abishek/OpenSPARCT1_model
(create the folder specified by the path represented by MODEL_DIR variable.}
CC_BIN=/usr/bin
(if not running in solaris system)
NCV_HOME=/import/EDAtools/ncverilog/ncverilog.v5.3.s2/5.x
(default path. change if required to change depending on the installation of NCverilog)
LM_LICENSE_FILE="/import/EDAtools/licenses/ncverilog_key"
(LM_LICENSE_FILE="/import/EDAtools/licenses/synopsys_key:/import/EDAtools/licenses/ncverilog_key")
PERL_CMD="/usr/bin/perl"
(if not running in solaris system)
PATH= (include only the necessary path variables, remove the rest)

4. Source the environment variables using
source OpenSPARCT1.bash

5. Depending on the system running the verification,  we have to create a symbolic link
cd $DV_ROOT/tools/env
ln -s Makefile.Linux.x86_64 Makefile.system (if it is a x86_64 cluster) what cluster are we using. mine is i686 system (uname -a)

5. change directory to the directory mentioned in the MODEL_DIR variable
cd /home/abishek/OpenSPARCT1_model

6. run the sims command to run the regression that is required (core1_full) in this case
sims -sim_type=ncv -group=core1_mini -novera_run -novera_build

7. Run the regreport command to get a summary of the regression
regreport $PWD/yyyy_mm_dd_ID > report.log

(the date on which the regression is done it is in the OpenSparcT1_MODEL directory created for this purpose)

B. Reference
README that comes along with the downloadables
OpenSPARC T1 Processor Design and Verification User's Guide
OpenSPARC T1 Processor External Interface Specification
OpenSPARC T1 Processor Datasheet
OpenSPARC T1 Processor Megacell Specification
OpenSPARC T1 Micro-Architecture Specification

NOTE :  Tried recompiling the libraries using mkplilib()  but ran into problems. I think the problems lie mainly with the 32 bit and 64 bit libraries and that I used debian linux and not opensolaris. So make sure when you are running the regression you use a Open Solaris system. 

Running Regression with ModelSIM - not solved but proceeds in the right direction. I feel would work on Open Solaris.

The SIMS command to be run
abishek@ubuntu:~/OpenSPARCT1_model$ sims -sim_type=mti -group=core1_mini -sim_build_cmd=/home/abishek/ModelSIM/modeltech/linux/vlog -sim_run_cmd=/home/abishek/ModelSIM/modeltech/linux/vsim -sim_build_args="-work /home/abishek/OpenSPARCT1_model/work" -sim_run_args=/home/abishek/OpenSPARCT1_model/work.cmp_top -novera_build -novera_run -novcs_run

Description - The simulation type is mti?
-sim_build_cmd - must point to the location of vlog compiler. this compiler is used to compile all the verilog files.
-sim_build_args -  contains the arguments that need to be passed to the vlog command.
-sim_run_cmd - used to open the vsim of MODELSIM
-sim_run_args -  arguments that are to be passed to the vsim command.

Error logs : solved
ERRORs
1.
In different blocks the same error
ERROR:Calling task $error outsideof action block is illegal
REASON: the function $error is not defined in MODELSIM. the alternate to $error is $display. $error is defined in synopsis tools. $display function is defined in MODELSIM 
SOLUTION:
sys.h
ifu.h
added the lines `define MODELSIM 1

2. Error: /home/abishek/OpenSPARCT1/design/sys/iop/srams/rtl/bw_r_rf16x160.v(646): Calling task $error outside of action_block is illegal.

http://opencores.org/websvn,filedetails?repname=sparc64soc&path=/sparc64soc/trunk/T1-common/srams/bw_rf_16x81.v&rev=2&isdir=0

`ifdef MODELSIM  
      $display ("sram_conflict", "conflict between read: %h and write: %h pointers", rd_a_ff, wr_a_ff);
`else
      $error ("sram_conflict", "conflict between read: %h and write: %h pointers", rd_a_ff, wr_a_ff);
`endif
also add a `define MODELSIM 1 in the beginning of this file.

Abishek Ramdas
NYU Poly

No comments:

Post a Comment