Saturday, March 5, 2011

6T SRAM Cell design, Implementation and Testing

A lot of text books are available which tell us the logical operation of 6T SRAM Cell. But only a few deal with the actual calculations of the widths of the transistors. I took up the challenge to design a 6T SRAM Cell from scratch.

The detailed report of my work in building a 6T SRAM incorporating the read and write conditions can be found using the following link.

https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0B4rJ5uMNHA9pMDZlNDU4ZjctODViYS00MWZhLThlNmYtMjcxNzllMzVjMGY1&hl=en&authkey=COiuv6EC

The schematic is tested using the test circuit shown in the circuit. Layouts are drawn using Cadence Virtuso. Was a great learning expeirence.

Abishek Ramdas
NYU Poly

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