Poly SPARC

Hello, Scan insertion is the process of converting the flip flops present in a circuit into scan flip flops The flip-flops in the circuit, shown in Figure, are connected together in a chain to form a shift register, also called scan chain. This makes all flip-flops in the circuit controllable and observable leaving behind only the combinational logic to be tested.  During scan mode, the test vectors are shifted into (scan-in) the scan chain by shift operations. The test vectors are then applied to the combinational logic and the response is clocked back into the flip-flops. The response is then shifted out (scan-out) from the scan chain to test as the next test vector is being scanned in. This DFT converts the difficult to test sequential circuit into a fully combinational circuit. For large designs, the long chain is split into several smaller chains in order to cope with the large number of test patterns. The chains can have different lengths and the depth is define...

Hello, I am posting an old program here that was written by me to trace different paths in a circuit. It is written in Perl and works for verilog (.v) files. The program recursively iterates through every path in the circuit and it prints out the gates encountered en-route.  It is useful if you are calculating a metric for each gate/wire This is a way to NOT write a program. The program, as I found out later, is very slow because It does not build the data structure for gates that makes traversing easier It works with gate names instead of numeric abstractions which are easier to deal with.  The better way to traverse through a circuit is to build a data structure for each gate encountered. Each gate should be assigned a number and there must be arrays in the data structure that holds information on the gates at its input and output. This makes traversing in both directions easier. Sample data structure struct gate{ char name[]; int num_in; int num_out; int i...

Hello , When working with benchmark circuits, it is convenient to levelize the gates and work with levels. This is useful when you want to calculate some metric for all gates or wires. It is efficient than recursively traversing through all wires, gates, and fanouts.  Here I upload a program that levelizes the iscas bench marks.  It is written in perl. Use it the way you see fit and edit it if you find mistakes. Levelization 1. Assign level number 0 to all primary inputs 2. For each PI fanout Label that circuit line with level number of the PI   Queue the logic gate driven by that fanout line (I need a queue) 3. While queue is not empty dequeue the next logic gate in the queue   If all of the gate fanins are labeled with level numbers, then label the logic gate and its fanouts with maximum of input levels + 1. Queue all fanouts of the logic gate. Otherwise requeue the logic gate.  Algorithm - Levelization loop inputlist ...