Tuesday, October 30, 2012

Synthesizing just the SPARC Core using design-vision

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You need to have successfully run rsyn - how?

Sparc has a number of blocks.
bw_clk_cl_sparc_cmp cpx_spc_buf cpx_spc_rpt exu ffu ifu lsu mul spu tlu spc_pcx_buf 
 
Steps are
1. collect all the flattened netlist files from each block in work folder

file_collect.sh - location design/sys/iop/sparc
cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/
for FILE in $(find . -type f | grep -e "flat")
do
echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files"
cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files
done

cd design/sys/iop/sparc
mkdir flat_files
./file_collect.sh

All the flat files in the sparc folder are present in /design/sys/iop/sparc/flat_files

2. collect the top level files from each of the blocks
you will find the top level blocks for each module in the rtl folder inside that module

current fldr - design/sys/iop/sparc/

1. sparc_ffu.v - ffu/rtl
2. sparc_ifu.v - ifu/rtl
3. sparc_exu.v - exu/rtl
4. lsu.v - lsu/rtl
5. tlu.v - tlu/rtl
6. spu.v - spu/rtl
7. sparc.v - ./rt/

copy these files into flat_files mentioned above.
Now all the required files are in flat_files folder.

1. Invoke design vision, run the configuration script to set up the libraries and work folders etc
2. File -> analyze, add all the files that are present in the work directory
3. File -> Elaborate, you will get warnings saying that sram modules (bw_r*) are missing, they cannot be synthesized because they are memory modules
4. Design -> compile
5. Command "report_qor > result_file" to report the area gate information etc.
6. Save the synthesized file. File -> save

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