Synthesizing just the SPARC Core using design-vision

-->

You need to have successfully run rsyn - how?
Sparc has a number of blocks.
bw_clk_cl_sparc_cmp cpx_spc_buf cpx_spc_rpt exu ffu ifu lsu mul spu tlu spc_pcx_buf 
 
Steps are
1. collect all the flattened netlist files from each block in work folder

file_collect.sh - location design/sys/iop/sparc
cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/
for FILE in $(find . -type f | grep -e "flat")
do
echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files"
cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files
done

cd design/sys/iop/sparc
mkdir flat_files
./file_collect.sh

All the flat files in the sparc folder are present in /design/sys/iop/sparc/flat_files

2. collect the top level files from each of the blocks
you will find the top level blocks for each module in the rtl folder inside that module

current fldr - design/sys/iop/sparc/

1. sparc_ffu.v - ffu/rtl
2. sparc_ifu.v - ifu/rtl
3. sparc_exu.v - exu/rtl
4. lsu.v - lsu/rtl
5. tlu.v - tlu/rtl
6. spu.v - spu/rtl
7. sparc.v - ./rt/

copy these files into flat_files mentioned above.
Now all the required files are in flat_files folder.

1. Invoke design vision, run the configuration script to set up the libraries and work folders etc
2. File -> analyze, add all the files that are present in the work directory
3. File -> Elaborate, you will get warnings saying that sram modules (bw_r*) are missing, they cannot be synthesized because they are memory modules
4. Design -> compile
5. Command "report_qor > result_file" to report the area gate information etc.
6. Save the synthesized file. File -> save

Comments

Post a Comment

Popular posts from this blog

Generating 16k ROM using Xilinx IP COREGEN and simulating it in modelsim

The instruction ROM is an IP Core. so before interfacing with the open8, it has to be generated. The method of generating and simulating a ROM Xilinx IP Core is described here. FIND ALL THE FILES HERE 1. app.coe (the initialization file) 2. rom_16k_core.vhd 3. rom_16k_core.vho 4. rom_16k_core.xco 5. top_level.vhd 6. do_memgen.do Creation of the ROM Xilinx 10.1 1. open ISE 2. create a new project 3. tools -> core generator(12.1) (or right click on the device and add a new file 10.1) 4. In the IP catalog -> Memory and storage elements -> RAM and ROM 5. double click on block memory generator, A new window opens 6. In the new window select single port ROM click next, Write first mode 7. Select Read Width = 8 and Read Depth = 16384 for 16K ROM -> next 8. The output ports are unregistered, load initialization COE if required -> next 9. No need to use the Reset pin -> next 10. Generate. (takes a little time then shows successfully generated) This
Read more

Setting up atalanta ATPG to work on Linux

Atalanta is an ATPG tool that is used to generate test patterns for combinational circuits. atalanta is a windows executable file. I am using Atalanta ATPG tool to generate the test patterns required for generating the Transition fault Test patterns RUNNING ATALANTA (LINUX) You need to have WINE installed to run windows executable binary. Created a symbolic link in the usr/bin to the atalanta.exe, name of the link s atalanta. (not necessary if you do not have root privilages) chmod u+x /place/atalanta/atalanta.exe cd /usr/bin sudo ln -s /place/atalanta/atalanta.exe ./atalanta COMMAND TO RUN ATALANTA atalanta [option] filename //put this in a shell script
Read more

Sparse matrix - 3 tuple representation

//program to 3-tuple representation #include<stdio.h> #include<unistd.h> #define SIZE 3000; void main() { int a[5][5],row,columns,i,j; printf("Enter the order of the matrix(5*5)"); scanf("%d %d",&row,&columns); printf("Enter the element of the matrix\n"); for(i=0;i<row;i++) for(j=0;j<columns;j++) { scanf("%d", &a[i][j]); } printf("3-tuple representation"); for(i=0;i<row;i++) for(j=0;j<columns;j++) { if(a[i][j]!=0) { printf("%d %d %d", (i+1),(j+1),a[i][j]); } } getchar(); }
Read more