Poly SPARC

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OpenSPARCT1 comes with a built in script called rsyn that is used to synthesize the required verilog files using synopsys design compiler. All the modules are individually compiled (except the mega cells) and you get the flattened and hierarchical verilog netlist file for individual modules.  You do not have the netlist file for the entire OpenSPARCT1 yet and that has to be done manually.   Important Scripts provided by SUN The OpenSPARCT1/design/sys/synopsys/script folder contains the scripts to configure and run synopsys   There are two configuration files     1. io configuration - project_io_cfg.scr     2. sparc configuration - project_sparc_cfg.scr  they contain the configuration information. Rsyn flow The rsyn command calls identifies the tool that is to be used and then calls the "rsyn,1.0" file in OpenSPARCT1/tools/perlmod 1. The rsyn file reads the block list that is present in OpenSPARCT1/design/sys/synopsys/. 2. It run...

It would be required to synthesize individual blocks in SPARC separately. For example, the method to synthesize the Load Store Unit is described here. You need to have successfully run rsyn - how? example lsu unit present in design/sys/iop/sparc/lsu Steps 1. Create a work folder anywhere you like 2. cd into design/sys/iop/sparc/lsu 3. Use the following script to collect the flat_files from the location 4. Use the following script to extract the flat nestlist from all modules inside lsu to a folder called flat_files Script: file_collect.sh (location /design/sys/iop/sparc/lsu) cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/lsu/flat_files done 5. copy the files that are present in ...

List of files to compile sparc core in design vision present in design/sys/iop/sparc/flat_files bw_clk_cl_sparc_cmp_flat.v lsu_stb_rwctl_flat.v sparc_ffu_ctl_flat.v sparc_ifu_invctl_flat.v spu_lsurpt_flat.v cpx_spc_buf_flat.v lsu_stb_rwdp_flat.v sparc_ffu_dp_flat.v sparc_ifu_mbist_flat.v spu_madp_flat.v cpx_spc_rpt_flat.v lsu_tagdp_flat.v sparc_ffu.v sparc_ifu_sscan_flat.v spu.v lsu_dcdp_flat.v lsu_tlbdp_flat.v sparc_ffu_vis_flat.v sparc_ifu_swl_flat.v tlu_hyperv_flat.v lsu_dctldp_flat.v lsu.v sparc_ifu_dcl_flat.v sparc_ifu.v tlu_incr64_flat.v lsu_dctl_flat.v sparc_exu_alu_flat.v sparc_ifu_dec_flat.v sparc_ifu_wseldp_flat.v tlu_misctl_flat.v lsu_excpctl_flat.v sparc_exu_byp_flat.v sparc_ifu_errctl_flat.v sparc_mul...

--> You need to have successfully run rsyn - how? Sparc has a number of blocks. bw_clk_cl_sparc_cmp cpx_spc_buf cpx_spc_rpt exu ffu ifu lsu mul spu tlu spc_pcx_buf    Steps are 1. collect all the flattened netlist files from each block in work folder file_collect.sh - location design/sys/iop/sparc cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/ for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/design/sys/iop/sparc/flat_files done cd design/sys/iop/sparc mkdir flat_files ./file_collect.sh All the flat files in the sparc folder are present in /design/sys/iop/sparc/flat_files 2. collect the top level files from each of the blocks you will find the top level blocks for each module in the rtl folder inside that module current fldr - design/sys...

If we are required to find area information or the routing information of the entire processor (with all 8 cores etc) we have to manually compile the flattened netlist file with the top level file of the processor. The procedure is described here. The top level module for OpenSPARCT1 is “iop.v” located at design/sys/iop/rtl Synthesize the whole processor using design vision I need the area information of the processor with all 8 cores 1. Run rsyn to generate all the flattened netlist - how? 2. collect all the flattened netlist file in a folder File: file_collect.sh Location ~/opt/OpenSPARCT1/flat_files cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files done 3. The top level file for the entire OpenSPARC chip is present in design/sy...

Configuration file for design_vision # synopsys_dc.setup file for opensparc # Define the lsi_10k library set SYN_LIBS /opt/synopsys/syn/libraries/syn set SPARC_INC /home/ar2654/opt/OpenSPARCT1/design/sys/iop/include # Define the libraries and search path set search_path [concat $search_path ${SYN_LIBS} ${SPARC_INC}] set target_library ${SYN_LIBS}/lsi_10k.db set link_library [concat "*" $target_library] set symbol_library ${SYN_LIBS}/lsi_10k.sdb define_design_lib WORK -path home/ar2654/opt/OpenSPARCT1/SYN_full/WORKar2654@nanovlsi % File: file_collect.sh cd /home/ar2654/opt/OpenSPARCT1/design/sys/iop for FILE in $(find . -type f | grep -e "flat") do echo "cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files" cp ${FILE} /home/ar2654/opt/OpenSPARCT1/flat_files done

  rsyn compiles all the files using design compiler. The default library used is lsi_10k.db Open Design and verification guide In the quick start section 1.3.1 follow unzip and untar commands cd to the folder untared Open the OpenSPARC.cshrc script Edit the document to set up the environment for openSPARC.cshrc synopsys libraries - /opt/synopsys/syn sparcos5 libraries - I was not able to find the libraries at the place mentioned in the document so I used to locate command to locate sparcos5 libraries locate sparcOS5 source the .tcshrc_synopsys file (it contains the license file in my case) source OpenSPARCT1.cshrc file rsyn -all If everything runs well you can find In the folder of every component (analog/*, ccx/* etc) you can find a folder called synopsys Inside that folder you will have log files for commands and design compiler A gate folder which contains the compiled, flattened and hierarchical ne...

# User needs to define these new variables setenv DV_ROOT /home/location_to/OpenSPARCT1 setenv MODEL_DIR /home/location_to/OpenSPARCT1_model if (`uname -s` == "SunOS") then setenv CC_BIN "/usr/dist/pkgs/sunstudio_`uname -p`/SUNWspro/bin" else setenv CC_BIN /usr/bin endif # Please define VERA_HOME only if you have VERA, otherwise comment it out. if ((`uname -s` == "SunOS") && (`uname -p` == "sparc")) then # setenv VERA_HOME /import/EDAtools/vera/vera,v6.2.10/5.x else # setenv VERA_HOME endif # Please define VCS_HOME only if you have VCS, otherwise comment it out. #setenv VCS_HOME /import/EDAtools/vcs/vcs7.1.1R21 # Please define NCV_HOME only if you have NC-Verilog, otherwise comment it out. #setenv NCV_HOME /import/EDAtools/ncverilog/ncverilog.v5.3.s2/5.x # Please define NOVAS_HOME only if you have Debussy, otherwise comment it out. if ((`uname -s` == "SunOS") && (`uname -p` == "sparc"))...

Here is an equivalent fault collapsing program, The aim is to  read a combinational Verilog netlist file and perform equivalent fault collapsing for the circuit. The program does equivalent fault collapsing for the following gate types Two-input, one-output gates or One-input, one-output gates as follows: AND2X1 OR2X1 NAND2X1 NOR2X1 XOR2X1 INVX1 BUFX1 Upgrade: Fanouts need to be considered separately. upgrade the program to include fanouts also #!/usr/bin/perl #fault_collapsing.plx use warnings; use strict; my $bench_file = $ARGV[0]; my $file_name; my $circuit_name; my $element; my @input_array; my @output_array; my @wire_array; my @gates; my @sorted_gates; my @wire_struct; #my @fanout_test; my $num_inputs=0; my $num_outputs=0; my $num_wires=0; my $num_gates=0; #Test netlist file if($bench_file =~ /(.*).v/) { $file_name = $1; } else { print "Format of bench file name: circuit_name.v \n example : s1...