Poly SPARC

WORKING WITH OPENPICIDE (Continuation of the tutorial which describes the setup of the software in ubuntu) How to open a new project 1. Project -> new project 2. In the window that pops up version -> fil as per requirements processor -> XIlinx picoblaze family Processor (tab) -> Picoblaze 3 (Note : Memory bank size = 1024 instruction. Rest is the default) compiler (tab) -> Entity name : prog_rom (Name of required output vhd/v file) VHDL template file : /location_of_kcpsm3/Assembler/rom_form.vhd Verilog template file : /location_of_kcpsm3/Assembler/rom_form.v sources -> if you have the assembly program ready put it here applicaiton -> editor options set as per user requirement NOTE IMPORTANT while writing the program 1. Certain syntaxes are different INPUT - IN OUTPUT - OUT RETURN - RET need to write a script to automate conversion. 2. "constants" syntax is different - yet to find out the new syntax (kindly let me kn...

Program - Transition fault testing using pattern shifting Serial version of the program is described here in detail This is the program i had written for testing delay transition faults. I am trying to parallelize this program. DELAY TESTING OBJECTIVE slow to raise and slow to fall patterns are to be tested. to test a slow to rise fault- apply a sa1 pattern (for a modified netlist) followed by a sa0 pattern (for unmodified netlist) to test a slow to fall fault - apply a sa0 pattern (for a modified netlist) followed by a sa1 pattern (for unmodified netlist)                      pattern 1   pattern 2  Slow to rise    sa1         sa0        Slow to fall    sa0         sa1    pattern 1 - patterns for modified netlist pattern 2 - patterns for unmodified netlist Testing for faults A. fault pattern ge...

Running a system level simulation of OpenSPARCT1 with ModelSIM Simulation of the opensparc is very important if you are going to understand its inner details. System level Simulation steps are given in the Design and verification guide chapter 6.7. The flow is to compile the libraries requried for simulation in ModelSIM and let the simulation scripts provided by the sparc people take care of simulating the system. Two sets of libraries are to be compiled. One for the ISE and the other for the EDK in the same order. The system requirements are Requirements ModelSIM SE/PE v6.5 is required to simulate XPS - 10.1.03 is required- If you have xilinx 10.1 to update it to 10.1.03 1. open xps 2. help -> about 3. If version is 10.1 4. help -> xilinx update 5. if version is 10.1.03 then you are allset RAM > 1.5 GB Compiling the libraries for modelsim in ISE source xilinx env variables source modelsim env variables 1. open a new project in ISE 2. Choose the device and...

Hi :) (: I was implementing a code in kcpsm assembly language for the picoblaze mc. Every time i had to test it, I had to dump it on the FPGA and look for the desired output. I dint have the time to search for a kcpsm simulator then so had to manage with the poor debugging capabilities and long dumping latencies for completing the assignment. More over KCPSM assembler that comes with the package, runs only in a windows environment. so i had to use DOSEMU everytime to just compile the program. All this sucked big time. So i went in search of a simulator/assembler for linux and then there was OPENPICIDE Open Pic IDE is open and supports linux windows mac and is downright amazing. Here i have included the steps to install and run openpicide in an UBUNTU system. Simulation of Picoblaze assembly code There are two tools to simulate picoblaze assembly language 1. openPICIDE 2. picoasm OpenPICIDE Integrated assembler development environment (IDE). Provides the following component...

Hi, I am working towards parallelization of one of my own sequential program. The sequential program is used to generate test patterns for Delay testing. (Testing of the rise and fall delays in a circuit). It takes up a lot of time to run and is a massively parallel program. So parallelization is a good idea to achieve speed up. I gathered a few points on parallelization of the program from the book "Parallel programming for Multicore and cluster systems" by Thomas Rauber Gudula Runger, I present them here. Aim: To parallelize the transition fault testing program so that it runs on more than one processor Steps involved in parallelization 1. Decomposition of the computations : GOAL : of task decomposition is keeping all the processors busy at all times. a. Computations of the sequential algorithm are decomposed into tasks and dependencies between the tasks are determined.Tasks are the smallest units of parallelism. b. Task may involve accesses to shared address s...

My dad is an amazing poet. I am posting here a few of his Poems. Enjoy :) A sense silently pervades. of solace ? the sense permeates. of fulfillment ? the deep crevices of my heart is filled with a serene sensation. solitude ? achievement ? i wonder... words ebb as slight pink baubles from the silent silvery lake of my mind, to burst forth on the canvas of the terminal, to converse with you of something tangible to me. a reaching is ma...

Truth and Lie decisions decisions choices that defines our lives that defines our goals and our means choices that define you. what is good and what is bad nobody really knows what is right and what is wrong both the definitions are lost in the entangled webs of self righteousness and practicality. none of them exist. pretty pictures in the minds of individuals, a hallucination for the begging soul to make believe. there are choices then there is the truth and there is the lie. choose wisely between the truth and the lie choose wisely who you are.

Purpose In life all things seem futile. the work being done, the events that occur. seems irrelevent to any condition random acts that seem to arise from the whim and fancy of the snake charmer. we dance in awkward steps to the barbaric noises from his drum going around in circles banality and platitude. experiences, situations, exercises, tests that seem to take us no where. progress?? no. hard work achieving what? no idea. stagnant sardonic and even ridiculous at times the pull is strong to stop the bull shit the utter futility in doing the job the laziness the lack of reason the lack of motivation sometimes it seems logical to just give up but know that what you see are just the dots unconnected dots spread around in space and time irrelevent and even irritating to the untrained eye. there is a grand picture that comes out of joining the dots. a beautiful plan unfolding slowly dots that can be connected. so hang in there when the dots are being la...

A lot of text books are available which tell us the logical operation of 6T SRAM Cell. But only a few deal with the actual calculations of the widths of the transistors. I took up the challenge to design a 6T SRAM Cell from scratch. The detailed report of my work in building a 6T SRAM incorporating the read and write conditions can be found using the following link. https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0B4rJ5uMNHA9pMDZlNDU4ZjctODViYS00MWZhLThlNmYtMjcxNzllMzVjMGY1&hl=en&authkey=COiuv6EC The schematic is tested using the test circuit shown in the circuit. Layouts are drawn using Cadence Virtuso. Was a great learning expeirence. Abishek Ramdas NYU Poly

Report on few techniques of Built In Self Test It was required of me to read and write a report on Built In Self Test. Reading and understanding the mathematical implications were very exciting. You can find the report in the following link https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0B4rJ5uMNHA9pNTkyODk2MjItN2QzZS00ZGIyLWE5NDgtZjZhMjIzMDZkNDBm&hl=en&authkey=CKHm7dQE Abishek Ramdas NYU Poly

Atalanta is an ATPG tool that is used to generate test patterns for combinational circuits. atalanta is a windows executable file. I am using Atalanta ATPG tool to generate the test patterns required for generating the Transition fault Test patterns RUNNING ATALANTA (LINUX) You need to have WINE installed to run windows executable binary. Created a symbolic link in the usr/bin to the atalanta.exe, name of the link s atalanta. (not necessary if you do not have root privilages) chmod u+x /place/atalanta/atalanta.exe cd /usr/bin sudo ln -s /place/atalanta/atalanta.exe ./atalanta COMMAND TO RUN ATALANTA atalanta [option] filename //put this in a shell script

MODELSIM - simulation of the sparc single core STEPS TO DO 1. create a working directory 2. open modelsim and create a library inside the working directory 3. after creating library open modelsim.ini file in an editor 4. search for Voptflow variable and change its value to 0 (Voptflow = 0) 5. add all the files inside OpenSPARCT1/design/sys/iop/sparc/xst/sparc.flist into the working directory 6. add all header files from the Opensparc/design/sys/iop/include into this folder 7. vlog *.v 8. vsim sparc.v The test benches are not known. I am in the process of identifying the test bench. :) Thought would dig into the EDK project into the MicroBlaze. One hell of a plan.

A. Running the regression.  Using NC Verilog simulator. core1_full regression. The core1 environment consists of one SPARC CPU core. 1. Download the OpenSPARCT1.tar.bz2 to the directory "/home/abishek/OpenSPARCT1" folder. 2. unzip and extract in the same folder 3. Set following environment variables in OpenSPARCT1.bash. comment out the rest DV_ROOT=/home/abishek/OpenSPARCT1 MODEL_DIR=/home/abishek/OpenSPARCT1_model (create the folder specified by the path represented by MODEL_DIR variable.} CC_BIN=/usr/bin (if not running in solaris system) NCV_HOME=/import/EDAtools/ncverilog/ncverilog.v5.3.s2/5.x (default path. change if required to change depending on the installation of NCverilog) LM_LICENSE_FILE="/import/EDAtools/licenses/ncverilog_key" (LM_LICENSE_FILE="/import/EDAtools/licenses/synopsys_key:/import/EDAtools/licenses/ncverilog_key") PERL_CMD="/usr/bin/perl" (if not running in solaris system) PATH= (include onl...

How to synthesize sparc.ngc (openSPARCT1) using Xilinx ISE IDE use Xilinx 10.1. compatibility issues witn Xilinx 12.2 The procedure was discussed by "formal guy" from the xilinx forum. But there were a few more parameters that needed to be set so that Open Sparc can be synthesized using the ISE. The method described below is tested. Here is a little more information on how to synthesize the T1 core manually from the ISE GUI. This is the procedure to follow if you can't use our automated scripts rsynp and rxil. (For exampe if you are on a Windows machine). From the start menu, select ISE -> Project Navigator From the Project Navigator GUI, select File->New Project ( the new project wizard may come up automatically if it is the first time you are running Project Navigator Select a project name and the project path Click next The next window is Device Properties: Select the correct Device, Package, and speed grade for your board. Click next The next w...

Here I briefly describe the documents that are important if you are starting with opensparc for the first time. I have added the description of the important folders.  If you are trying to do synthesis, regression, diag tests read the OpenSPARC DV GUIDE . Most important resource. IMPORTANT DOCUMENTS IN THE RUNNING OF RXIL     1. README: file :This file must be read initially and specifies the values to the environment variables that are to be sourced.     2. OpenSPARCT1.bash (or) OpenSPARCT1.csh : script : are the scripts where the environment variables are actually initialized. Depending on your shell, one of these files are modified and sourced.     3. Xilinx12.1.sh: script :This script is used to initialize the locations of the xilinx tools that are required to run rxil and create NGC and V files. Commnet out lines that are not required by you.     4. Rxil: script : it is a script that check the env variables se...

RXIL 1.# PERL SCRIPT FLOW OF CONTROL by Abishek Ramdas NYU Poly SYNOPSYS          The RXIL1.2 version of the perl script is described here. This perl script is invoked by the rxil command followed by paramenters for xilinx synthesis. Visit the design and verification guide for details on running the rxil command for xilinx.      The rxil command is located inside OpenSPARCT1/tools/bin/rxil. It is a bash script. There are different versions of rxil (perl script) if you look inside OpenSPARCT1/tools/perlmod/ (ex rxil,1.0 ,rxil,1.1 ,rxil,1.2). rxil bash script is used to find the latest version of rxil perl script and transfer control to that script. This bash script calls the  configsrch script to searcg for the latest configuration of rxil. ( it executes configsrch rxil /). It is also used to identify the machine and set the environment variable PERL5OPT according to the machine. This script then calls the current ver...

Abishek Ramdas - Resume https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0B4rJ5uMNHA9pNzVjZjU1ZjEtNGEyYy00YzEyLTkyYWUtM2M0Y2NiN2MyZThj&hl=en&authkey=COvhuOoH Detailed Report on Parallel Version of Sobol Quasi Random Number Generator : https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0B4rJ5uMNHA9pZTA0MjI3YjYtOTgzYi00M2ZhLTk3NDUtOGNiMGQ2MmQ4M2Vh&hl=en&authkey=CPypsogJ Report on Built In Self Test https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0B4rJ5uMNHA9pNTkyODk2MjItN2QzZS00ZGIyLWE5NDgtZjZhMjIzMDZkNDBm&hl=en&authkey=CKHm7dQE 6T SRAM Cell Design and Test https://docs.google.com/viewer?a=v&pid=explorer&chrome=true&srcid=0B4rJ5uMNHA9pMDZlNDU4ZjctODViYS00MWZhLThlNmYtMjcxNzllMzVjMGY1&hl=en&authkey=COiuv6EC

Sobol Quasi Random Number Generaotors Sobol Quasi Random Number Generaotors (sobol QRNG) are pseudo random number generators. There are often applications, for example in financial engineering, where random numbers are to be generated within an upper and lower limit. The main requirement of the random numbers to be generated in these applications are that the random numbers must fill the N space more uniformly than uncorrelated random points. The serial algorithm for Sobol QRNG can be found at " Implementation of Sobol Quasi Random Number generator “sobseq()” Chapter 7.7, Numerical Recepies in C, http://www.nrbook.com/a/bookcpdf.php " I have used pthreads to parallelize the algorithm. The main idea is "Divide and Conquer". If 64000 patterns are to be generated by 4 threads then each thread generates 64000/4 = 16000 random numbers. The catch is that each thread must be provided with an intial seed so that no two threads generate the same set of random numbe...

Hi, I have started working on Multicore Programming. The subject is fascinating because all the super computers are multicored (obviously). Multicore is introducing a paradigm shift in computing. Earlier Clock frequencies were increased to achieve a higher speed. But a point has been reached where increasing the clock frequencies are bound to give diminishing returns because of increased leakage and heating. So to keep up with Moore's law speed up is achieved by parallelizing the program and running it on multiple cores (Amdahl's law). It is a point of consideration that most of the programs are serial by nature and the parallelize-able portion is very small when compared to the serial portion. so one might argue that there might not be significant speed up. But consider a massively parallel machine which runs the same program on different sets of data. It offers a definite advantage to run them simultaneously on different sets of data. That is what i believe multicore progr...

Here is the general procedure that is followed to burn an assembly code onto the Pico Blaze MC. 1. Write your own ROM program by learning the PicoBlaze instruction sets.   2.  Compile  the  program  to  VHDL  by  using  KCPSM  assembler  (This assembler  requires  32­bit  operating  system) 3. Synthesize the VHDL program and the PicoBlaze soft code in ISE. 4. Generate bit file (You also need to include your modified UCF file).   5. Download the bit file to the FPGA and check if that works. You can find the detailed procedure in the manual that comes along with the downloads (last post). Read page 40 of the KCPSM manual on how to use the KCPSM assembler. STEP BY STEP PROCEDURE Problem Statement : Run the following  assembly program on the FPGA Board (we dont care about the output just  burning the program onto the soft MC) loop : INPUT s2,00     ...

Bit of an Intro to PicoBlaze .... PicoBlaze is the designation of a series of three free soft processor cores from Xilinx  for  use  in  their  FPGA  and  CPLD  products.  They  are  based  on  a  RISC architecture of 8 bits and can reach speeds up to 100 MIPS on the Virtex 4 FPGA's family. The processors have an 8‐bit address and data port for access to a wide range of peripherals. The license of the cores allows their free use.   The hardware is synthesised using the HDL processor and the assembler generated PROM and can be is placed and routed on an FPGA. once this is done, the FPGA acts as a processor executing the instructions that are stored in the PROM one after the other. They can be used in typical embedded applications such as weather monitoring station, robotic control, home automation, washing machine, microwave controller. The advantage is any number of digital custom blocks can be connecte...

So I was asked to write a few programs as a homework assignment. Was really simple but was a good exercise with the assembly codes. ARM Assembly Home Work 2 Date 02/10/11 Abishek Ramdas 1. x = (a+b);     ADR r4, a        ;get address of variable 'a'     LDR r0, [r4]    ;load the valuf of 'a' into r0. r0 <- a     ADR r4, b        ;get address of b into r4     LDR r1, [r4]     ;r1 <- b     ADD r3, r1, r0  ;r3 <- a+b     LDR r4, x         ;get addres of x into r4     STR rs, [r4]      ;x <- (a+b) 2. y = (c-d) + (e-f)     ADR r4, c     LDR r0,[r4]        ;r0 <- c     ADR r4, d     LDR r1, [r4]    ...

I was looking for some assembly language simulators for ARM. Open sources preferable (free!) so after a lot of trial and error,  I found that QEMU was the solution I was looking for. here is a short description  of QEMU. "QEMU is a generic and open source machine emulator and virtualizer. When used as a machine emulator, QEMU can run OSes and programs made for one machine (e.g. an ARM board) on a different machine (e.g. your own PC). When used as a virtualizer, QEMU achieves near native performances by executing the guest code directly on the host CPU. QEMU supports virtualization when executing under the Xen hypervisor or using the KVM kernel module in Linux. When using KVM, QEMU can virtualize x86, server and embedded PowerPC, and S390 guests." (source : http://wiki.qemu.org/Main_Page ) We dint have a simulation environment set up in our school for running ARM programs. So i decided to get myself one because i knew there were a number of open sourced hardware ...

ARM DOCUMENTATION Note : These are the steps i followed in setting up to develop C programs for ARM using the GNU tool chain. I am not using this currently, I am using an ARM emulator called QEMU. IDE     eclipse COMPILER     gcc DEBUGGER     gdb SIMULATOR     insight REFERENCES http://download.ronetix.info/toolchains/arm/arm_cross_development_guide.pdf (contains the files that are to be downloaded for simulator) http://embeddedcraft.org/armtutorials.html ERROR arm-elf-insight: error while loading shared libraries: libexpat.so.0: cannot open shared object file: No such file or directory cd /lib ln libexpat.so.1 libexpat.so.0 this error is removed after this -------------------------------------------- INSTALLING ECLIPSE 1. synaptic package manager 2. search eclipse 3. mark and apply for installation after it is installed you have to install the eclipse c/c++ development tool chain In package mana...