OpenSPARC - Synthesis of OpenSPARC using Xilinx ISE - Abishek Ramdas
How to synthesize sparc.ngc (openSPARCT1) using Xilinx ISE IDE
use Xilinx 10.1. compatibility issues witn Xilinx 12.2
The procedure was discussed by "formal guy" from the xilinx forum. But there were a few more parameters that needed to be set so that Open Sparc can be synthesized using the ISE. The method described below is tested.
Here is a little more information on how to synthesize the T1 core manually from the ISE GUI. This is the procedure to follow if you can't use our automated scripts rsynp and rxil. (For exampe if you are on a Windows machine).
From the start menu, select ISE -> Project Navigator
From the Project Navigator GUI, select File->New Project ( the new project wizard may come up automatically if it is the first time you are running Project Navigator
Select a project name and the project path
Click next
The next window is Device Properties:
Select the correct Device, Package, and speed grade for your board.
Click next
The next window is Create new source.
Just skip this and click next
The next window is Add existing Source
Just skip this and click next
Finish the Wizard to create the project.
Now search for the following file which is a source list for the sparc core:
design/sys/iop/sparc/xst/sparc.flist
You need to select add sources and add each file from the file list to the project.
Note that you may need to copy files ending with .behV to a new name ending with .v so that ISE recognizes the files a Verilog files.
The next step is to set the compile time macros: To do this:
(make sure "sparc" is the top module)
1. Look for the ISE sub-window on the left labeled "Processes"
2. Find the "Synthesize-XST" entry in that window
3. Right click on that entry and select "Properties"
4. In the popup window "Process Properties - Synthesis Options,
select "synthesis options in the left window
5. Set the property display level to "Advanced"
6. In the right list scroll down to find the property
"Verilog Macros"
7. Type the value FPGA_SYN FPGA_SYN_1THREAD FPGA_SYN_NO_SPU FPGA_SYN_8TLB in that box.
8. now DESELCT "process->properties->xilinx specification options->add i/o buffers"
Finally Run synthesis:
From the Processes window, right-click on Synthesize-XST and select Run in the popup Menu.
Error Logs:
Error1 : cannot find verilog module sys.h
Solution
so adding all the library files - tlu.h, sys.h, sys_paths.h, lsu.h, iop.h, ifu.h, xst_defines.h from /design/sys/include
ERROR2: cannot find bw_r_irf_register
Solution
maybe because of changing the top module. changing it back to bw_r_irf_register and running synthesis. synthesis of bw_r_irf_register completed successfully. changing the top module to sparc.v and trying again.
Synthesis Successful ran for more than half an hour.
Error3: Adding sparc.ngc into the EDK, the process fails with following "warnings"
INFO: NgBuild:889 - Pad Net '<something>' is not connected to external port in this design. A new port '<somethiing else>'is added and is connected to this signal
Solution
You need to resynthesise the sparc.ngc. Follow the steps given above and make sure you do step 8. DESELCT "process->properties->xilinx specification options->add i/o buffers"
Ignoring this step causes the sparc.ngc to be synthesised properly but fail during the EDK process.
Abishek Ramdas
NYU Poly
use Xilinx 10.1. compatibility issues witn Xilinx 12.2
The procedure was discussed by "formal guy" from the xilinx forum. But there were a few more parameters that needed to be set so that Open Sparc can be synthesized using the ISE. The method described below is tested.
Here is a little more information on how to synthesize the T1 core manually from the ISE GUI. This is the procedure to follow if you can't use our automated scripts rsynp and rxil. (For exampe if you are on a Windows machine).
From the start menu, select ISE -> Project Navigator
From the Project Navigator GUI, select File->New Project ( the new project wizard may come up automatically if it is the first time you are running Project Navigator
Select a project name and the project path
Click next
The next window is Device Properties:
Select the correct Device, Package, and speed grade for your board.
Click next
The next window is Create new source.
Just skip this and click next
The next window is Add existing Source
Just skip this and click next
Finish the Wizard to create the project.
Now search for the following file which is a source list for the sparc core:
design/sys/iop/sparc/xst/sparc.flist
You need to select add sources and add each file from the file list to the project.
Note that you may need to copy files ending with .behV to a new name ending with .v so that ISE recognizes the files a Verilog files.
The next step is to set the compile time macros: To do this:
(make sure "sparc" is the top module)
1. Look for the ISE sub-window on the left labeled "Processes"
2. Find the "Synthesize-XST" entry in that window
3. Right click on that entry and select "Properties"
4. In the popup window "Process Properties - Synthesis Options,
select "synthesis options in the left window
5. Set the property display level to "Advanced"
6. In the right list scroll down to find the property
"Verilog Macros"
7. Type the value FPGA_SYN FPGA_SYN_1THREAD FPGA_SYN_NO_SPU FPGA_SYN_8TLB in that box.
8. now DESELCT "process->properties->xilinx specification options->add i/o buffers"
Finally Run synthesis:
From the Processes window, right-click on Synthesize-XST and select Run in the popup Menu.
Error Logs:
Error1 : cannot find verilog module sys.h
Solution
so adding all the library files - tlu.h, sys.h, sys_paths.h, lsu.h, iop.h, ifu.h, xst_defines.h from /design/sys/include
ERROR2: cannot find bw_r_irf_register
Solution
maybe because of changing the top module. changing it back to bw_r_irf_register and running synthesis. synthesis of bw_r_irf_register completed successfully. changing the top module to sparc.v and trying again.
Synthesis Successful ran for more than half an hour.
Error3: Adding sparc.ngc into the EDK, the process fails with following "warnings"
INFO: NgBuild:889 - Pad Net '<something>' is not connected to external port in this design. A new port '<somethiing else>'is added and is connected to this signal
Solution
You need to resynthesise the sparc.ngc. Follow the steps given above and make sure you do step 8. DESELCT "process->properties->xilinx specification options->add i/o buffers"
Ignoring this step causes the sparc.ngc to be synthesised properly but fail during the EDK process.
Abishek Ramdas
NYU Poly
Excellent tutorial, it was very helpful!
ReplyDeleteThe following should be consider when including the header files:
ISE does not use the project files to find the `include files for Verilog. So in essence adding sys.h to the project only gives you a convenient way to open it for editing. For include files that are not in the project directory you need to add the path to the Verilog Include Directories under the Synthesis Properties settings. If you use a command line flow the switch you need is -vlgincdir
The Synthesis Properties dialog box allows you to browse to the directory to select it.