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Setting up atalanta ATPG to work on Linux

Atalanta is an ATPG tool that is used to generate test patterns for combinational circuits. atalanta is a windows executable file. I am using Atalanta ATPG tool to generate the test patterns required for generating the Transition fault Test patterns RUNNING ATALANTA (LINUX) You need to have WINE installed to run windows executable binary. Created a symbolic link in the usr/bin to the atalanta.exe, name of the link s atalanta. (not necessary if you do not have root privilages) chmod u+x /place/atalanta/atalanta.exe cd /usr/bin sudo ln -s /place/atalanta/atalanta.exe ./atalanta COMMAND TO RUN ATALANTA atalanta [option] filename //put this in a shell script
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Transition Fault Testing using pattern shifting - The sequential Pseudocode

Program - Transition fault testing using pattern shifting Serial version of the program is described here in detail This is the program i had written for testing delay transition faults. I am trying to parallelize this program. DELAY TESTING OBJECTIVE slow to raise and slow to fall patterns are to be tested. to test a slow to rise fault- apply a sa1 pattern (for a modified netlist) followed by a sa0 pattern (for unmodified netlist) to test a slow to fall fault - apply a sa0 pattern (for a modified netlist) followed by a sa1 pattern (for unmodified netlist)                      pattern 1   pattern 2  Slow to rise    sa1         sa0        Slow to fall    sa0         sa1    pattern 1 - patterns for modified netlist pattern 2 - patterns for unmodified netlist Testing for faults A. fault pattern ge...
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Generating 16k ROM using Xilinx IP COREGEN and simulating it in modelsim

The instruction ROM is an IP Core. so before interfacing with the open8, it has to be generated. The method of generating and simulating a ROM Xilinx IP Core is described here. FIND ALL THE FILES HERE 1. app.coe (the initialization file) 2. rom_16k_core.vhd 3. rom_16k_core.vho 4. rom_16k_core.xco 5. top_level.vhd 6. do_memgen.do Creation of the ROM Xilinx 10.1 1. open ISE 2. create a new project 3. tools -> core generator(12.1) (or right click on the device and add a new file 10.1) 4. In the IP catalog -> Memory and storage elements -> RAM and ROM 5. double click on block memory generator, A new window opens 6. In the new window select single port ROM click next, Write first mode 7. Select Read Width = 8 and Read Depth = 16384 for 16K ROM -> next 8. The output ports are unregistered, load initialization COE if required -> next 9. No need to use the Reset pin -> next 10. Generate. (takes a little time then shows successfully generated) This...
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