Setting up ARM Simulation Environment using GNU Tool chain

ARM DOCUMENTATION

Note : These are the steps i followed in setting up to develop C programs for ARM using the GNU tool chain. I am not using this currently, I am using an ARM emulator called QEMU.

IDE
    eclipse
COMPILER
    gcc
DEBUGGER
    gdb
SIMULATOR
    insight

REFERENCES
http://download.ronetix.info/toolchains/arm/arm_cross_development_guide.pdf
(contains the files that are to be downloaded for simulator)
http://embeddedcraft.org/armtutorials.html

ERROR
arm-elf-insight: error while loading shared libraries: libexpat.so.0: cannot open shared object file: No such file or directory

cd /lib
ln libexpat.so.1 libexpat.so.0

this error is removed after this
--------------------------------------------
INSTALLING ECLIPSE
1. synaptic package manager
2. search eclipse
3. mark and apply for installation

after it is installed you have to install the eclipse c/c++ development tool chain
In package manager search
eclipse cdt and install
----------------------------------------------------------------------------

TO SETUP THE INSIGHT SIMULATOR INSIDE ECLIPSE
http://embeddedcraft.org/freearmtools3a.html#top

1. Run -> external tools -> external tools configuration

2. click on the Lunch new configuration button

3. Name it "insight"

4. Location is /home/abishek/opt/ARM/bin/arm-elf-insight

5. select the work bench

6. Now go to the common tab of External Tools Configurations and configure it to be displayed in External Tools favorites menu.
------------------------------------------------------------------------------

HELLO WORLD PROGRAM
http://blogs.arm.com/software-enablement/139-hello-world-in-assembly/
http://www.armadeus.com/wiki/index.php?title=Eclipse


setting up arm tools
http://embdev.net/articles/Using_arm-elf-run
using C to write ARM tools






Comments

Post a Comment

Popular posts from this blog

Setting up atalanta ATPG to work on Linux

Atalanta is an ATPG tool that is used to generate test patterns for combinational circuits. atalanta is a windows executable file. I am using Atalanta ATPG tool to generate the test patterns required for generating the Transition fault Test patterns RUNNING ATALANTA (LINUX) You need to have WINE installed to run windows executable binary. Created a symbolic link in the usr/bin to the atalanta.exe, name of the link s atalanta. (not necessary if you do not have root privilages) chmod u+x /place/atalanta/atalanta.exe cd /usr/bin sudo ln -s /place/atalanta/atalanta.exe ./atalanta COMMAND TO RUN ATALANTA atalanta [option] filename //put this in a shell script
Read more

Sparse matrix - 3 tuple representation

//program to 3-tuple representation #include<stdio.h> #include<unistd.h> #define SIZE 3000; void main() { int a[5][5],row,columns,i,j; printf("Enter the order of the matrix(5*5)"); scanf("%d %d",&row,&columns); printf("Enter the element of the matrix\n"); for(i=0;i<row;i++) for(j=0;j<columns;j++) { scanf("%d", &a[i][j]); } printf("3-tuple representation"); for(i=0;i<row;i++) for(j=0;j<columns;j++) { if(a[i][j]!=0) { printf("%d %d %d", (i+1),(j+1),a[i][j]); } } getchar(); }
Read more

Generating 16k ROM using Xilinx IP COREGEN and simulating it in modelsim

The instruction ROM is an IP Core. so before interfacing with the open8, it has to be generated. The method of generating and simulating a ROM Xilinx IP Core is described here. FIND ALL THE FILES HERE 1. app.coe (the initialization file) 2. rom_16k_core.vhd 3. rom_16k_core.vho 4. rom_16k_core.xco 5. top_level.vhd 6. do_memgen.do Creation of the ROM Xilinx 10.1 1. open ISE 2. create a new project 3. tools -> core generator(12.1) (or right click on the device and add a new file 10.1) 4. In the IP catalog -> Memory and storage elements -> RAM and ROM 5. double click on block memory generator, A new window opens 6. In the new window select single port ROM click next, Write first mode 7. Select Read Width = 8 and Read Depth = 16384 for 16K ROM -> next 8. The output ports are unregistered, load initialization COE if required -> next 9. No need to use the Reset pin -> next 10. Generate. (takes a little time then shows successfully generated) This...
Read more