Simulation of a single core of OpenSPARCT1


MODELSIM - simulation of the sparc single core

STEPS TO DO
1. create a working directory
2. open modelsim and create a library inside the working directory
3. after creating library open modelsim.ini file in an editor
4. search for Voptflow variable and change its value to 0 (Voptflow = 0)
5. add all the files inside OpenSPARCT1/design/sys/iop/sparc/xst/sparc.flist into the working directory
6. add all header files from the Opensparc/design/sys/iop/include into this folder
7. vlog *.v
8. vsim sparc.v

The test benches are not known. I am in the process of identifying the test bench. :) Thought would dig into the EDK project into the MicroBlaze. One hell of a plan.

Comments

Popular posts from this blog

Setting up atalanta ATPG to work on Linux

Generating 16k ROM using Xilinx IP COREGEN and simulating it in modelsim

Sparse matrix - 3 tuple representation