Sunday, April 17, 2011

INTERFACE BETWEEN Open8 and MEM

A 256 byte memory model is described in VHDL to using on chip BRAM for testing on FPGA board. It is interfaced with the Open8 soft processor. It is used as both program memory and data memory. The program can be loaded in binary into the memory, interfaced with open8 and can be simulated using modelsim.


1. Using the BRAM in the FPGA board as program memory/Data memory.

Memory Size
open8 has 16 bit address lines. I have implemented a 256 byte RAM (Uses the internal BRAM of the spartan3 FPGA) to connect it to the FPGA.

The memory entity is described below

-----------------------------------------------------------------------------
-- Memory: RAM
-- Desc: Instruction/ data memory
-- no of entries : 256 bytes
-- no of bits    : 8
-- we - write enable
-- re - read enable
-- en - select memory
-- addr - address(8 bits)
-- di - data in  (8 bits)
-- do - data out (8 bits)
------------------------------------------------------------------------------


entity RAM_NC is 
  port (
    clk  : in  std_logic;
    en   : in  std_logic;
    we   : in  std_logic;                     -- write enable provided en = 1
    re   : in  std_logic;                     -- enable signal for read
    addr : in  std_logic_vector(7 downto 0);  -- address 8 bits
    di   : in  std_logic_vector(7 downto 0);  -- data input 8 bits
    do   : out std_logic_vector(7 downto 0));
end RAM_NC;
This will serve as my program memory. The open8 processor starts executing from address 144 in the memory (PC=0000000010010000). So load program from that address.


The entity of the open8
component Open8_CPU
    port (
      Clock : in std_logic;
      Reset                    : in  std_logic;
      CPU_Halt                 : in  std_logic;
      Interrupts               : in  INTERRUPT_BUNDLE;
      --
      Address                  : out ADDRESS_TYPE;
      Rd_Data                  : in  DATA_TYPE;
      Rd_Enable                : out std_logic;
      Wr_Data                  : out DATA_TYPE;
      Wr_Enable                : out std_logic );
  end component;

Structurally connect the following lines
MEM CPU
addr <- Address(7 downto 0)
we   <- Wr_Enable
re    <-  Rd_Enable
do   <-  Rd_Data
di    <-  Wr_Data
en   <-  Address(15)

The open8 has an assembly code reference manual from where you can get the binary codes you need to load into the memory. I loaded a simple test program into the memory (location 144 onwards).


OPEN8 - MEMORY INTERFACE
FILES
1. Open8.vhd can be downloaded from www.opencores.org
2. Open8_pkg.vhd can be downloaded from www.opencores.org
3. RAM.vhd - Memory module
4. Open8_MEM.vhd - Interface between the memory and open8 processor (TOP LEVEL)
5. do_open8.do - do simulation file


Compile the VHDL files and run to do file to get the simulation
Note the instructions are read in the rd_data input and the value of the alu_regs changing according to the instruction under execution. 



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